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Using a buffer to modify an input port

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mahmood.n

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May I ask why the following code doesn't work?

Code:
entity test is
	port( a: buffer std_logic_vector(2 downto 0);
				clk: in std_logic);
end;
architecture my of test is
begin			 																				
	process( clk )
	begin
	    if (clk'event and clk = '1') then
                 a <= a(1 downto 0) & '0';	
  	    end if;
	end process;
end;

If a=011 then the value of a won't change over the clock.
 

Well I want to modify the input value, e.g. add with 1 or shift by n bit. with "in" type, it is not allowed.
 

Why would you modify an input? It is coming in, not going out, so whats going to read it?>
 

Buffer type is an output. The circuit has no input other than clk.
 

Well assume the input port receives a number (std_logic_vector) and I want to manipulate it. The following doesn't work either


Code:
entity test is
	port( a: in std_logic_vector(2 downto 0);
			clk: in std_logic;
			z: out std_logic_vector(2 downto 0));
end;

architecture my of test is 
	signal tmp : std_logic_vector(2 downto 0) := a;
begin			 																								process( clk )
	begin
		if (clk'event and clk = '1') then
                  tmp <= tmp(1 downto 0) & '0';	
  	end if;												 
	z <= tmp;
	end process;
end;
 

Code:
signal tmp : std_logic_vector(2 downto 0) := a;
That initialized tmp at the time of synthesis for power up only. (in ASIC synthesis it is ignored)

You have to assign a to tmp using an if statement and some control signal to signal you are loading tmp with the a input.

e.g.

Code VHDL - [expand]
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process (clk)
begin
  if rising_edge(clk) then
    if (load_a = '1') then
      tmp <= a;
    else
      tmp <= tmp(1 downto 0) & '0';
    end if;
  end if;
end process;
z <= tmp;

 

You have to assign a to tmp using an if statement and some control signal to signal you are loading tmp with the a input.
OK I understand that. That method is works as I tested.

Apart from the synthesis issues and rules of variable vs. signal, I wonder why using variable doesn't fully work! I know it doesn't make sense, but at least I have to see a working code!
Code:
entity test is
	port( a: in std_logic_vector(2 downto 0);
			clk: in std_logic;
			z: out std_logic_vector(2 downto 0));
end;

architecture my of test is 
begin			 																				process( clk )
		variable tmp: std_logic_vector(2 downto 0) := a;
	begin
		if (clk'event and clk = '1') then
			tmp := tmp(1 downto 0) & '0';		 
			z <= tmp;
		end if;												 
	end process; 
end;
But z is not valid in the first three cycles as picture shows.
 

Attachments

  • wave.jpg
    wave.jpg
    30.2 KB · Views: 82

update

I think you are still suffering from a conceptual misunderstanding of how VHDL code represents the physical gate level design of digital circuits. Unless you code things like multiplexers (if statements, or case statements) you won't have logic to load a register.

Maybe you should pick up a copy of HDL Chip Design by Douglas Smith, which has nice side by side code of both VHDL and Verilog along with gate level output of a synthesis tool for the code.

- - - Updated - - -

Yeah it's invalid because z is never assigned anything until the '0' is shifted through.

- - - Updated - - -

I really can't stomach code with variables used as registers.
 
Here, tmp is initialised to a at time zero. At time zero, A is "UUU" (which is what tmp would have been if not assigned an initial value).

Hence why you see 'U' on the Z port for 3 cycles before '0' propgates. After 3 clocks, Z will always be 0. The a input here is redundant and unused.
 

Here, tmp is initialised to a at time zero. At time zero, A is "UUU" (which is what tmp would have been if not assigned an initial value).

Hence why you see 'U' on the Z port for 3 cycles before '0' propgates. After 3 clocks, Z will always be 0. The a input here is redundant and unused.

Well the variable has been initialized. Thing is that, instead of initializing to a constant value, e.g. "000", I wrote a. If I use "000", then the output in the first three cycles become zero.

You said that
That initialized tmp at the time of synthesis for power up only. (in ASIC synthesis it is ignored)
, so I thought such thing is valid for signals only and variables should accept such initialization. Thanks.
 

You can't initialize using a non-constant value it is ignored by synthesis tools, I'm somewhat surprised it didn't throw an error or warning.

Hmm, you did look at the warnings, critical warnings, errors generated by the tools...
 

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