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How to add extra hold time slack?

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sitawman

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Hi!, I did place and route of a design and for the hold-time slack i got 0ns, but it says it met the timing. But when i read the design in primetime, then read sdc and spef, i get a hold-time slack of -0.27ns, is there anyway i can add extra slack during place and route, make it more than 0ns? or even if not during place and route, maybe in synthesis? I use DC and ICC. Thanks!
 

you can use "set_clock_uncertainty -hold ..." or set_path_margin. But, it will be better to fully understood what is the reason of such discrepancy. Maybe, something wrong with tools setup?
 
you can use "set_clock_uncertainty -hold ..." or set_path_margin. But, it will be better to fully understood what is the reason of such discrepancy. Maybe, something wrong with tools setup?

don't use uncertainty for hold, that's not right. you need to set a global hold target. in cadence innovus the command
setOptMode -setupTargetSlack somevalue
setOptMode -holdTargetSlack somevalue

Also, to OP: 270 ps is a big difference, depending on which technology you are working on. In 16nm, that would be the equivalent of 10+ inverters. Maybe your setup doesn't match.
 
sitawman asked for ICC commands.

Use uncertainty - it is common practice. It is also recommended by the foundry (TSMC).
 

Hi! thank you for your responses. I tried setting the clock as propagated and the slack became -0.01ns. Can I do that? Or that should always be the case? Thanks!
 

Hi again ! I read the man page of set_path_margin and I did not understand the description. What does this command do? Does is set target slack? Also I noticed that it has -to and -from arguments, does that mean I have to declare it on every violating path? Is there a way i can use it more generally, like set a value for the whole design? Thanks!
 

After CTS you should set clock as propagated (especially in final timing analysis).

Regarding set_path_margin - it set additional margin on some paths (not the whole design). Additional means: if you have zero slack, after applying this command you will have negative slack, so the tool will try to extra optimize the specified path. The options -from/-to help you to specify the paths that need to be aggressively optimized. It is the same notation as you have in report_timing command.
 
After CTS you should set clock as propagated (especially in final timing analysis).

Regarding set_path_margin - it set additional margin on some paths (not the whole design). Additional means: if you have zero slack, after applying this command you will have negative slack, so the tool will try to extra optimize the specified path. The options -from/-to help you to specify the paths that need to be aggressively optimized. It is the same notation as you have in report_timing command.

Hi! I checked my sdc from pnr and the clock was already set as propagated there. I checked my timing analysis and the problem is the clock network delay for my launch register is 0, while for my capture register i have some value. That is why I get hold time violarions. Is it possible to have 0 clock network delay or this should not be the case? Thanks again!
 

Try report_time -path_type full_clock_expanded for your problem path. And see the clock network to your startpoint. Is it buffered?

Did you set clock as propagated in primetime? (you should read "clock network delay (propagated)" in the timing report).
 

    V

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Hi! The design now passes timing analysis. But its weird. When i do remove_design -all then rerun the script it fails sta, but when i do remove_design -all and remove_lib -all then rerun the script it passes sta. Which is correct and which is wrong? Why do they have different results? The script does, loading of libraries, reading the design, linking, reading sdc and spef.. Thanks!
 

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