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    Xilinx ISE problem - RAM implemented as distributed instead of block

    Hello everyone,
    As you can see in the title , i have a problem with a memory that I infer as block RAM but it is implemented as distributed leading to excessive resources being used.
    The error showing up in Xilinx XST is the following :
    INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features.

    The read operation of the RAM is (pretty much ) this one :
    Code Verilog - [expand]
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    always @(posedge clk) begin
                        if ( counter < 972 ) begin  // RAM <banks> has 972 banks of 5 bits each
                            read_reg <= banks[counter][max_error_bits -1 : 0];
                            counter <= counter + 1;
                        end
    begin
    If i understand correctly , the tool says that i read from the memory asynchronously but i am pretty sure i do it synchronously. Is there something that i am missing?

    Thank you in advance,
    Nikos
    Last edited by ads-ee; 11th September 2017 at 22:21. Reason: added syntax tags

    •   Alt10th September 2017, 20:19

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    Re: Xilinx ISE problem - RAM implemented as distributed instead of block

    what about the write?

    perhaps it is the declaration (eg, using 972 or 1024 vs 1023) or the extra [max_error_bits-1:0]. I think the latter is ok and the former is not ok. ISE is really bad at explaining why something isn't a BRAM.



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    Re: Xilinx ISE problem - RAM implemented as distributed instead of block

    The write operation is also in the same always block, but it is a bit more complicated that's why i dont include it. The important thing is that i write only at 1 address per clock cycle, so that shouldnt be a problem for the RAM to be interpreted as distributed.
    Anyway, back to the read operation, do you suggest to change the depth to a power of 2 ( 1023 for example ) and write to/read from the first 972 addresses?

    Thank you



    •   Alt10th September 2017, 20:39

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    Re: Xilinx ISE problem - RAM implemented as distributed instead of block

    I've had issues in the past with something like [0:1024] not being detected as any type of BRAM, while [0:1023] would be detected correctly.



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    Re: Xilinx ISE problem - RAM implemented as distributed instead of block

    Well, i changed the vector declaration to : [width-1 : 0 ] banks [ 0 : 1023 ] ( where width=5 ) and still got the same problem. Any other ideas?



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    Re: Xilinx ISE problem - RAM implemented as distributed instead of block

    This post on the Xilinx forum has the template produced for an inferred RAM in XST. (I don't have XST installed so can't verify).
    https://forums.xilinx.com/t5/Synthes...ST/td-p/221553

    Code Verilog - [expand]
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    always @(posedge <clock>) begin
          if (<enableA>) begin
             if (<write_enableA>)
               <ram_name>[<addressA>] <= <input_dataA>;
               <output_dataA> <= <ram_name>[<addressA>];
          end
          if (<enableB>)  <output_dataB> <= <ram_name>[<addressB>];
       end
    The takeaway here is there is no complicated comparisons or other code in the template. Just simple enableA and enableB placeholder. I would avoid having anything but a single signal name in those <xxxxxx> spots. Having comparisons and other signals (e.g. counter) buried within your inferred RAM code is more likely to result in problems.

    Also on that page I referenced is the use of the RAM_STYLE attribute, which can force the type of inferred RAM used.



    •   Alt11th September 2017, 22:30

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  7. #7
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    Re: Xilinx ISE problem - RAM implemented as distributed instead of block

    you could try using only one index: "read_reg <= banks[counter]" and then resize the bus in an assign statement outside of the always block.

    and also double check that the ram isn't accessed anywhere else -- eg in simulation-only code.



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