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    Solving hold time problems via SDC only

    Hello,

    FPGA A is connected to FPGA B via a source synchronous parallel bus - 8 data lines and 1 clock.
    FPGA A asserts data with a tco of 0.5ns from the positive clock edge to data valid.
    However, the system has a design flow: The clock line that connects FPGA A and B is passed through a buffer while the data lines don't.

    This buffer causes the clock to be delayed for 2 ns - essentially changing the tco FPGA B sees to a negative value.

    I solved the problem with a PLL via changing the phase of the input clock to a safe value.


    But can such problem be solved via SDC only ?
    I.E: tell the timing tools that I'm expecting a negative propagation delay and have it solve the problem...

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    Re: Solving hold time problems via SDC only

    Change the the input delay constraint for the data based on the skew on the clock. That is the usual way of specifying constraints on source synchronous input interfaces.


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    •   Alt10th September 2017, 17:27

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    Re: Solving hold time problems via SDC only

    Change the the input delay constraint for the data based on the skew on the clock.
    So, you're suggesting not to use a PLL and simply change the input delay to a negative value ?

    - - - Updated - - -

    I've attached a drawing illustrating the timing violation caused by the addition of the buffer (only on the clock line).
    I solved it by adding a phase shift of 270 degrees using a PLL inside FPGA B.

    You're saying that I could've solved it by SDC only without the PLL?



    •   Alt10th September 2017, 19:14

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    Re: Solving hold time problems via SDC only

    So, you're suggesting not to use a PLL and simply change the input delay to a negative value ?
    Yes it can be done via SDC only. Analyze the violating paths the timing tool reports and accordingly set the set_input_delay and/or set_output_delay for DDR interfaces.
    .....yes, I do this for fun!


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    •   Alt10th September 2017, 20:19

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    Re: Solving hold time problems via SDC only

    Suppose that because of the PCB buffer, the positive clock edge arrives 3nS after the data is valid.

    How would the set_input_delay command look like?



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    Re: Solving hold time problems via SDC only

    Suppose that because of the PCB buffer, the positive clock edge arrives 3nS after the data is valid.
    How would the set_input_delay command look like?
    When your clock and data enters the FPGA, you want the data to be transiting with the rising edge of the clock, right?

    If so, then as you have clock skew of 3ns, then one way would be to delay the data also by 3ns, which can be achieved by the SC command:
    set_input_delay -clock [get_clocks your_input_clk] -min <min_delay_value_in_ns> [get_ports {data_port_name}]
    set_input_delay -clock [get_clocks your_input_clk] -max <max_delay_value_in_ns> [get_ports {data_port_name}]
    The max and min values can be set by analyzing the timing path.
    .....yes, I do this for fun!


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    Re: Solving hold time problems via SDC only

    When your clock and data enters the FPGA, you want the data to be transiting with the rising edge of the clock, right?
    You would want to ensure that data transitions only after hold time is met...

    I suspect the clock delay via buffer was intentional at some point.



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    Re: Solving hold time problems via SDC only

    I suspect the clock delay via buffer was intentional at some point.
    The buffer is there for I/O protection only.
    The board designer simply forgot to also add a buffer on the data lines - and now it causes an unbalanced clock-data delay.

    When your clock and data enters the FPGA, you want the data to be transiting with the rising edge of the clock, right?

    If so, then as you have clock skew of 3ns, then one way would be to delay the data also by 3ns, which can be achieved by the SC command:
    set_input_delay -clock [get_clocks your_input_clk] -min <min_delay_value_in_ns> [get_ports {data_port_name}]
    set_input_delay -clock [get_clocks your_input_clk] -max <max_delay_value_in_ns> [get_ports {data_port_name}]
    The max and min values can be set by analyzing the timing path.
    The values marked in red will have to be negative - correct ?



    •   Alt11th September 2017, 16:26

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    Re: Solving hold time problems via SDC only

    The values marked in red will have to be negative - correct ?
    They are allowed to take negative values.

    You have the timing analysis report, in there look at the failing data path and accordingly put the delay on the data path.
    .....yes, I do this for fun!


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