rafimiet
Member level 5
After synthesizing, I get the static timing report as follows
I am using Finite State Machine of over 600 lines. Throughout the code I have tried my level best to minimize the combinational path delay using registers wherever required. Now I have a combinational delay of 3.189ns, which is acceptable. Can I know what delays are taken into consideration when calculating minimum period? Is there anything that I can do to increase the Maximum Frequency of my design? (So far I have not provided any constraints to the clock)
Code:
Minimum period: 7.577ns (Maximum Frequency: 131.987MHz)
Minimum input arrival time before clock: 2.325ns
Maximum output required time after clock: 2.826ns
Maximum combinational path delay: 3.189ns