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  1. #1
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    verilog code for creating and deleting of clock error.

    hi,

    I am having a problem with writing Verilog code for creation of clock error and deletion of clock error.

    thank you

    •   Alt8th September 2017, 11:20

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  2. #2
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    Re: verilog code for creating and deleting of clock error.

    Thats a shame. How are you going to fix it? and what does your post even mean?



    •   Alt8th September 2017, 11:36

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  3. #3
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    creating and deleting error due to clock

    thank you tricky dicky,

    I meant error due clock like jitter or skew. i have to create a data transmission error due to noise or clock skew or voltage level



    •   Alt8th September 2017, 12:08

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  4. #4
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    Re: verilog code for creating and deleting of clock error.

    I am having a problem with writing Verilog code for creation of clock error and deletion of clock error.
    Don't expect that here! No one would do your homework here.

    You should explain your situation and problem properly.
    Have you tried something on your own? What problems do you face?
    Do you have a model in mind so as to generate an ERROR-ED clock (rectifying the problem can be done later)?

    Thats a shame. How are you going to fix it? and what does your post even mean?
    lol...
    .....yes, I do this for fun!



  5. #5
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    creating and deleting error due to clock

    thank you dpaul.

    I have an idea to implement but I don't know how to start the coding.



    •   Alt9th September 2017, 05:13

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  6. #6
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    Re: creating and deleting error due to clock

    Usually, I open a text editor and start mashing my fingers on the keyboard.



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