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  1. #1
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    Do functions and procedures infer registers in VHDL?

    Functions and procedures are used to define often repeated sequence of instructions on data into a single place like in any other language. Is it true that in VHDL they are only able to infer combinatorial logic and never any registers? Is this true even if they are called from a process under rising_edge(clk) being true?

    Is there no way for them to infer registers at all?

    •   Alt7th September 2017, 16:23

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    Re: Do functions and procedures infer registers in VHDL?

    you would not usually infer registers from them directly, just how they are used.
    If they are used inside a clocked process, then assuming they synthesise, they will infer registered logic. Technically here, the function/procedure have only infered logic, with the clocked process infering the register.

    A function can NEVER infer a register on it's own, because a function cannot have timing inside it, and it always completes within a single delta.
    But I believe it is possible to infer a register from a procedure. For example, the following procedures should infer a register when compiled:

    Code VHDL - [expand]
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    procedure reg(signal clk : in  std_logic; 
                  signal d   : in  std_logic;
                  signal q   : out std_logic ) is
    begin
      if rising_edge(clk) then
        q <= d;
      end if;
    end procedure;
     
    -- this should also infer a register (if synth tool supports wait until in process, which most do if there is only 1)
    procedure reg(signal clk : in  std_logic; 
                  signal d   : in  std_logic;
                  signal q   : out std_logic ) is
    begin
      wait until rising_edge(clk);
      q <= d;
    end procedure;
    ...
     
    architecture rtl of my_ent is
    begin
      reg(clk, ent_ip, ent_op);
    end architecture rtl;

    This works because code not inside a process actually infer a process, sensitive to all "input" signals.

    so this line:

    a <= b;

    is actually this process:

    Code:
    process(b)
    begin
      a <= b;
    end process;



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