Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Difference between SCMOS and Vendor native Design Kits in MOSIS

Status
Not open for further replies.
B

bio_man

Full Member level 2
Joined
Mar 30, 2010
Messages
144
Helped
2
Reputation
4
Reaction score
4
Trophy points
1,298
Activity points
2,698

Attachments

  • MOSIS_account.png
    MOSIS_account.png
    58.2 KB · Views: 102

See "Processes That Also Support SCMOS Rules":
SCMOS_vs_vendor-specific_rules.png

Use SCMOS for simplicity or portability of design means the design rules are a common subset of different similar (i.e. same process size) processes, possibly of different fabs/foundries. Hence they are not so strict as the vendor-specific rules.

Hence use SCMOS rules, if you want just a few chips (for design evaluation, on an MPW or on a single/few wafer(s)) or if you plan to possibly transfer your design to another process.

Use vendor-specific rules if you plan for high volume chip production (min. 1 wafer lot, ≈24 wafers). These rules are more strict and allow for denser (smaller) designs.
 
The problem is that when I submit an inquiry to MOSIS asking about the availability of native nMOS transistor in C5, they advised me to initiate an account and pointed out that it may be available in native vendor PDK. Now, I have my layout for the whole circuit prepared using SCMOS PDK, it seems I can't just include the native nMOS if I got the vendor PDK which means I need to redo the layout !! right? This is at least what I understand from this link : https://www.mosis.com/pages/design/rules/index

- - - Updated - - -

here is a screenshot:
MOSIS.png

- - - Updated - - -

and FYI, I am doing a prototype for my circuit which means SCMOS is much better to use.
 

SCMOS comes from a time when scaling was somewhat linear, you would just shrink the dimensions but gates would remain more or less similar. this is no longer true, e.g., finfets. No idea why MOSIS still keeps it in there, or why you would try to do a modern circuit using it.
 
bio_man said:
I am doing a prototype for my circuit which means SCMOS is much better to use.
Click to expand...
In this case you must renounce on native nMOS. Anyway, it's not sure that ON semi offers native nMOS in their C5 process. At least I don't know.

ThisIsNotSam said:
this is no longer true, e.g., finfets. No idea why MOSIS still keeps it in there
Click to expand...
We're talking of an ancient 0.5µm process. Still going strong, at least for design evaluation and prototyping on MPW wafers via MOSIS, Europractice ... on a regular basis.
still_going_strong.jpg
 

ThisIsNotSam said:
SCMOS comes from a time when scaling was somewhat linear, you would just shrink the dimensions but gates would remain more or less similar. this is no longer true, e.g., finfets. No idea why MOSIS still keeps it in there, or why you would try to do a modern circuit using it.
Click to expand...

For me, it is just a proof of concept for a circuit that I designed
 

bio_man said:
For me, it is just a proof of concept for a circuit that I designed
Click to expand...

why not an FPGA then? what is your design?

even when we want to prototype some custom design 'on the cheap', we use TSMC 65nm around here. 500nm technology is so... OLD.
 

ThisIsNotSam said:
why not an FPGA then? what is your design?

even when we want to prototype some custom design 'on the cheap', we use TSMC 65nm around here. 500nm technology is so... OLD.
Click to expand...

you are right, it is old but it is funded by MOSIS through their educational program. I can't afford paying for fabrication. BTW, how much cheap is TSMC 65nm? for example, 500nm is around $1000/1mm2 without packaging.

- - - Updated - - -

ThisIsNotSam said:
why not an FPGA then? what is your design?
Click to expand...

It is DC-DC converter intended for power management in energy harvesting circuits.
 

last time we paid ~5k for 1 mm^2 of TSMC 65nm. with packaging.
 

I am not aware of C5 having native FETs, but other
ON flows (like ONC18) do have nvt (~0) and lvt (~0.3).
I have participated in ONC18 multiproject runs (for
ROICs) through ON directly (not MOSIS). You ought to
reach out to them, bypassing MOSIS, to see about the
economics.

ONC18 variant I was working with has 3.3V I/O devices
and 1.8V "core" devices. There may be a 5V I/O option,
I do not know - project was not interested in 5V.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top