Vijay Vinay
Member level 5
Hello guys,
I have designed a frequency divider for my thesis design. I am getting quite compromising results for my design. However, there are some overshoots in my design output. I am using a vpulse clock as my input. I am not sure, why there are certain overshoots. It would be helpful if you help me in solving this issue. I have attached the design of the frequency divider as well as its output. Thanks in advance.
I have designed a frequency divider for my thesis design. I am getting quite compromising results for my design. However, there are some overshoots in my design output. I am using a vpulse clock as my input. I am not sure, why there are certain overshoots. It would be helpful if you help me in solving this issue. I have attached the design of the frequency divider as well as its output. Thanks in advance.
