Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

design of 8 bit shift register in cadence virtuoso

Status
Not open for further replies.
T

tisheebird

Member level 5
Joined
Feb 23, 2017
Messages
88
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
662
Hello everyone.

I have to design a 8 bit Shift register in cadence virtuoso by using bus. I have made 1 bit SR and now planning to simulate the same 8 bit SR with same 1-bit SR. I don't need to cascade 8 1-bit SR.

Just one time and it should automatically repeat.


Please tell me with the steps:


Cheers.
 

If you have a single bit shift register SR:

8-bit-shift_register.png

The connectivity results from the io signal's bit order inherently.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top