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using modelsim with tsmc 0.18u library

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tanish

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hello
can anyone give me a hand about using modelsim with tsmc 0.18u library?
I wanna use modelsim as my verilog code simulator and I wanna have timing analysis of my code in modelsim with tsmc 0.18u.
if it is possible can anyone tell me how?
and send me the essential files.
 

I wanna use modelsim as my verilog code simulator and I wanna have timing analysis of my code in modelsim with tsmc 0.18u.
Click to expand...

Modelsim is used for simulation only.
The tsmc 0.18u library comes into picture when you are synth your design.

So refer to your synthesis tool docu as to how tsmc 0.18u library can be used with it.
 

but I saw somewhere that we can define other libraries for modelsim but I can't remeber.
actually I'm not sure that it works for my case or not.
 

simulation is not the best tool to do timing analysis with. your synthesis tool is the best approach.
 

I know Its not the best way but It can be useful to know the timing analysis approximately during simulation before synthesis.
I have a pdf file that describes the area and delay of all gates in tsmc 0.18 u technology file but I wanna know that does any library file available for it to use it in modelsim?
for example for and 2 :
Capture1.PNG
Capture2.PNG
 

tanish said:
I know Its not the best way but It can be useful to know the timing analysis approximately during simulation before synthesis.
I have a pdf file that describes the area and delay of all gates in tsmc 0.18 u technology file but I wanna know that does any library file available for it to use it in modelsim?
Click to expand...
So you are telling us that you intend to do you entire design using gates from the library instead of behavioral RTL code?


1. HDLs using Verilog, VHDL, Catapult C, etc are used to create behavioral descriptions.
2. Behavioral descriptions are synthesized into library primitives by the synthesis tool using timing constraints.
3. Now you have a gate level description where you could use the gate level simulation models from your vendor to do grossly inaccurate timing simulations.
4. Gate level simulation is slow.
 
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tanish said:
I know Its not the best way but It can be useful to know the timing analysis approximately during simulation before synthesis.
Click to expand...

Not really. This is a terrible idea.
 

your answer was convincing but I have another question,why gate level simulation is slow?
 

tanish said:
your answer was convincing but I have another question,why gate level simulation is slow?
Click to expand...

something like a 32-bit compare is just simulating this behaviorally...
Code: 
if (a == b) ....

the gate level representation of this is perhaps 100 lines of instantiated components.

The more stuff you have to simulated the slower the simulation is going to be...
 
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