+ Post New Thread
Results 1 to 4 of 4
  1. #1
    Newbie level 6
    Points: 1,031, Level: 7

    Join Date
    Jul 2012
    Posts
    14
    Helped
    0 / 0
    Points
    1,031
    Level
    7

    Shift register will parallel load

    How can design shift register with parallel load...................

    •   Alt5th September 2017, 13:17

      advertising

        
       

  2. #2
    Super Moderator
    Points: 236,416, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    40,889
    Helped
    12494 / 12494
    Points
    236,416
    Level
    100

    Re: Shift register will parallel load

    1. Decide about the intended function like asynchronous or synchronous load
    2. Write a behavioral description from the scratch
    or
    3. Copy the gate level circuit of a respective logic IC, e.g. 74165, 74166.



    •   Alt5th September 2017, 14:06

      advertising

        
       

  3. #3
    Super Moderator
    Points: 27,697, Level: 40
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    6,323
    Helped
    1535 / 1535
    Points
    27,697
    Level
    40

    Re: Shift register will parallel load

    You already have code for an up/down counter with preload, modify it for shifting...
    Code Verilog - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    37
    38
    39
    40
    41
    42
    43
    44
    45
    
    module preload_counter(q,
                           clk,
                           rst,
                           en,
                           load,
                           preload,
                           upd
                           );
                           
    input clk,rst,load,upd,en;
    input [2:0] preload;
    integer c;
    output [2:0] q;
    reg [2:0] q;
     
    always @(posedge clk)
    begin
       if (rst)     
         q <= 3'b000;
     
        else if (load)
            q <= preload;
           else if(upd)
           // else
          begin
             q <= q + 1;
             if( q == 3'b111)
               begin
               c = 1'b1;
               $display("Counter is full count = %b and c = %d",q,c);
               end
             end
           else 
             begin
             q <= q - 1;
             if( q == 3'b000)
               begin
               c = 1'b0;
               $display("Counter is empty count = %b and c = %d",q,c);
               end
           end
    end
             
     
    endmodule

    Just change the lines for q <= q + 1 and q <= q - 1 to perform a shift left/right instead of an increment/decrement.

    FYI as I never code with blocking assignments inside a edge triggered always block, I can't be absolutely sure, but I think c might end up as a latch since it isn't defined in all branches of the if statement and will therefore have to be held at whatever state it was last, i.e. it becomes a latch.



    •   Alt5th September 2017, 15:36

      advertising

        
       

  4. #4
    Full Member level 6
    Points: 3,477, Level: 13
    Achievements:
    7 years registered
    vipinlal's Avatar
    Join Date
    Mar 2010
    Location
    India
    Posts
    354
    Helped
    76 / 76
    Points
    3,477
    Level
    13

    Re: Shift register will parallel load

    Quote Originally Posted by sandy2811 View Post
    How can design shift register with parallel load...................
    I have posted here a code for PISO(parallel in serial out) few years back. Its in VHDL though, but in both behavioral and structural methods.
    Last edited by ads-ee; 8th September 2017 at 15:35. Reason: personal blog site link deleted
    If we admit that human life can be ruled by reason, then all possibility of life is destroyed.



--[[ ]]--