Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Formal verification with don't touch cell

Status
Not open for further replies.

Johannah

Newbie level 6
Joined
Apr 11, 2017
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
102
Good Day!

How do I perform formal equivalence checking if one of my module is set to don't touch since I instantiated directly a standard cell on it. When I add this module to Reference Tab, it cannot be link to the top module. Can you please tell me the proper step. Thanks a lot.
 

set_dont_touch is an implementation trick, it should not stop any verification effort. you are doing something wrong.
 

I dont think set_dont_touch settings have anything to do with FV
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top