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synthesis question about generated clocks

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sitawman

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Hi, if for example i have two clocks then they are connected to a mutiplexer, should i declare the output as a generated clock?
 

not needed. just make different sdcs and use set_case_analysis for each clock mode
 
If you set in DC variable timing_enable_multiple_clocks_per_reg to true, the tool will time the registers with both clocks. So, it will save runtime - you have timing for both clocks in on session (do not need to switch set_case_analysis). But, you may have timing from one clock to the other - call them asynchronous or set false path between them. It's up to you.
 

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