+ Post New Thread
Results 1 to 13 of 13
  1. #1
    Junior Member level 1
    Points: 1,091, Level: 7

    Join Date
    Jul 2012
    Posts
    17
    Helped
    0 / 0
    Points
    1,091
    Level
    7

    Counter Preload by any given values

    Hello,
    How can preload the counter by known value......counter is either synchronous or asynchronous.
    if i want to start my counter from 5 then which type of coding is required in verilog....

  2. #2
    Advanced Member level 4
    Points: 7,096, Level: 20
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    1,030
    Helped
    233 / 233
    Points
    7,096
    Level
    20
    Blog Entries
    1

    Re: Counter Preload by any given values

    Synchronous logic will be better. I won't give you codes, but hints.

    1st do you know how to write code for a simple synchronous up or down counter?

    If no, then 1st learn how a simple synchronous counter can be coded with Verilog (Google search will give you 100's of results).

    If yes, then you can modify that slightly to allow loading of values from an external port. Keep a single bit input port named such as counter_load_i. Depending on the counter start value to be loaded (for your case it is 5), keep provision for another multi-bit input port through which you can load this value.

    Now on the rising edge of your clock, check if your counter_load_i is HIGH (this signal should be high only when you want to load the particular start value, else low). So if it is high, load the value (5) from the external multi-bit input port to an internal register, on the clock rising edge. Next increment/decrement that internal register on the clk rising edge. There...your system is done!
    .....yes, I do this for fun!


    1 members found this post helpful.

    •   Alt1st September 2017, 11:11

      advertising

        
       

  3. #3
    Advanced Member level 4
    Points: 5,363, Level: 17

    Join Date
    Apr 2016
    Posts
    1,128
    Helped
    202 / 202
    Points
    5,363
    Level
    17

    Re: Counter Preload by any given values

    Quote Originally Posted by sandy2811 View Post
    Hello,
    How can preload the counter by known value......counter is either synchronous or asynchronous.
    if i want to start my counter from 5 then which type of coding is required in verilog....
    forget asynchronous. make it synchronous. add a reset signal or a load signal that can make the counter value assume e.g. 5
    Really, I am not Sam.



  4. #4
    Member level 1
    Points: 899, Level: 6

    Join Date
    Dec 2013
    Posts
    36
    Helped
    0 / 0
    Points
    899
    Level
    6

    Re: Counter Preload by any given values

    use a synchronous counter with reset value 5



  5. #5
    Junior Member level 1
    Points: 1,091, Level: 7

    Join Date
    Jul 2012
    Posts
    17
    Helped
    0 / 0
    Points
    1,091
    Level
    7

    Re: Counter Preload by any given values

    I have already done this things as you have told, but i want to reset it by using preset or clear logic but i am not getting it perfectly...............



  6. #6
    Super Moderator
    Points: 54,942, Level: 57
    Achievements:
    7 years registered
    Awards:
    Most Frequent Poster 3rd Helpful Member

    Join Date
    Apr 2014
    Posts
    11,126
    Helped
    2615 / 2615
    Points
    54,942
    Level
    57

    Re: Counter Preload by any given values

    Hi,

    Show your code.
    Then it's more easy to see what (and how) you have done so far...and to give detailled code modifications.

    Klaus



    •   Alt4th September 2017, 07:09

      advertising

        
       

  7. #7
    Junior Member level 1
    Points: 1,091, Level: 7

    Join Date
    Jul 2012
    Posts
    17
    Helped
    0 / 0
    Points
    1,091
    Level
    7

    Re: Counter Preload by any given values

    Quote Originally Posted by KlausST View Post
    Hi,

    Show your code.
    Then it's more easy to see what (and how) you have done so far...and to give detailled code modifications.

    Klaus
    My code is this


    [syntax=verilog]module preload_counter(q,
    clk,
    rst,
    en,
    load,
    preload,
    upd
    );

    input clk,rst,load,upd,en;
    input [2:0] preload;
    integer c;
    output [2:0] q;
    reg [2:0] q;

    always @(posedge clk)
    begin
    if (rst)
    q <= 3'b000;

    else if (load)
    q <= preload;
    else if(upd)
    // else
    begin
    q <= q + 1;
    if( q == 3'b111)
    begin
    c = 1'b1;
    $display("Counter is full count = %b and c = %d",q,c);
    end
    end
    else
    begin
    q <= q - 1;
    if( q == 3'b000)
    begin
    c = 1'b0;
    $display("Counter is empty count = %b and c = %d",q,c);
    end
    end
    end


    endmodule[/syntax]
    Last edited by FvM; 4th September 2017 at 08:28. Reason: Added syntax tags



  8. #8
    Member level 1
    Points: 899, Level: 6

    Join Date
    Dec 2013
    Posts
    36
    Helped
    0 / 0
    Points
    899
    Level
    6

    Re: Counter Preload by any given values

    I'm sorry what is exactly the problem in this code ?



  9. #9
    Junior Member level 1
    Points: 1,091, Level: 7

    Join Date
    Jul 2012
    Posts
    17
    Helped
    0 / 0
    Points
    1,091
    Level
    7

    Re: Counter Preload by any given values

    Nothing problem in this code but my idea is to make a counter which is start by a given or known value( i assume 5).
    and i want to start counter by this (5) initial value by using preset or clear input.



  10. #10
    Advanced Member level 4
    Points: 7,096, Level: 20
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    1,030
    Helped
    233 / 233
    Points
    7,096
    Level
    20
    Blog Entries
    1

    Re: Counter Preload by any given values

    I have already done this things as you have told, but i want to reset it by using preset or clear logic but i am not getting it perfectly...............
    In common terminology, a clear input drives a flop to a reset state (this would be similar to what your are doing with the rst signal).
    A preset input drives a flip-flop to a set state, and I guess you want the counter value to be 5 when a preset signal is asserted. So just add a sync check for another input signal 'preset' which, if high, will drive q to value 5.

    I recommend you to read and understand this:
    http://www.csit-sun.pub.ro/courses/M.../hdlcode6.html
    .....yes, I do this for fun!



  11. #11
    Member level 3
    Points: 2,333, Level: 11

    Join Date
    Nov 2006
    Posts
    59
    Helped
    6 / 6
    Points
    2,333
    Level
    11

    Re: Counter Preload by any given values

    Sandy2811, in the code you provided, you need to change the "always @(posedge clk)" to be "always @(posedge rst or posedge clk)" to see the effect of "rst" in simulation



  12. #12
    Advanced Member level 4
    Points: 7,096, Level: 20
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    1,030
    Helped
    233 / 233
    Points
    7,096
    Level
    20
    Blog Entries
    1

    Re: Counter Preload by any given values

    Sandy2811, in the code you provided, you need to change the "always @(posedge clk)" to be "always @(posedge rst or posedge clk)" to see the effect of "rst" in simulation
    The OP might be modeling a sync reset, we don't know, so he maybe correct!
    .....yes, I do this for fun!



    •   Alt6th September 2017, 16:36

      advertising

        
       

  13. #13
    Junior Member level 1
    Points: 1,091, Level: 7

    Join Date
    Jul 2012
    Posts
    17
    Helped
    0 / 0
    Points
    1,091
    Level
    7

    Re: Counter Preload by any given values

    Quote Originally Posted by sherif123 View Post
    Sandy2811, in the code you provided, you need to change the "always @(posedge clk)" to be "always @(posedge rst or posedge clk)" to see the effect of "rst" in simulation
    Thanks but i have design this for synchronous reset.....



--[[ ]]--