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bulk connections to different nodes in CMOS

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bio_man

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Hi,

Is there any way to connect bulk connection of same-type transistors (nMOS or pMOS) to different voltage nodes in one layout?

for example, I attached here two nMOS transistors. I want to connect bulk1 to V1 and bulk2 to V2, not that V1 and V2 are not the same.

thanks
 

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  • Bulk_layout.png
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If they are in the same (p-)substrate, it's not possible.

Should you have a triple well process (p-well in n-well in p-substrate), you can create nMOS transistors in separate p-wells with different bulk voltages. Similarly as with pMOS transistors in separate n-well bulks.
 
And of course SOI gives you a free hand in this
respect.
 
Unfortunately it seems C05 (CMOS 0.5um ) is an n-well and doesn't support triple well.

SOI = Silicon-On-Insulator, right? looks like another technology not same as CMOS. Is that right?
 

CMOS, on insulating handle wafer. Some foundries have
common frontside processing and a choice of plain, epi
or thick film SOI (like TowerJazz CA18). I do not know
what C05 offers or why you want to independently bias
device bodies.

I have used CA18HB which has 5V devices and is SOI.
There are about 20 CA18 flow variants, maybe 4 of them
SOI. I've even gotten SOI mixed in with JI wafers on the
multiproject runs.

Check with your foundry about flow variants. Who sets
the technology, anyway?
 
CMOS, on insulating handle wafer. Some foundries have
common frontside processing and a choice of plain, epi
or thick film SOI (like TowerJazz CA18). I do not know
what C05 offers or why you want to independently bias
device bodies.

I have used CA18HB which has 5V devices and is SOI.
There are about 20 CA18 flow variants, maybe 4 of them
SOI. I've even gotten SOI mixed in with JI wafers on the
multiproject runs.

Check with your foundry about flow variants. Who sets
the technology, anyway?

My project is part of my study, I've selected the CN05 (or C5, they are the same) because it can be funded by MOSIS for research purposes. Here is a description about the technology ( https://www.mosis.com/vendors/view/on-semiconductor/c5 )
They mentioned that they support EPI wafers, what is the difference between EPI and non-EPI?

I want to have control over the bulk connections so I can usually connect the bulk to source (Vsb=0) to run away from body voltage nonlinearity that increases Vth because I've bunch of flying transistors where sources are not connected to gnd neither VDD for pMOS. Actually, I simulated my circuit twice, one time with all bulk/source tied together (Vsb=0) and it worked as expected. Then, I count the body connection by connecting all bulk terminals to either gnd or VDD (nMOS or pMOS) and then the circuit did not work. So, I have two options now:
1) get control over bulk connections and always connect them to sources, which is something looks unfeasible in CN05 technology.
2) redesign the circuit accounting for Vsb being not zero.
 

2) redesign the circuit accounting for Vsb being not zero.

Yes. For the bunch of flying NMOS transistors where sources are not connected to gnd you could use native NFETs (Vth≈0). As they are stacked at positions higher than gnd, they can easily be closed down (OFF), and also don't need much more gate control voltage for the ON state than their normal NFET brothers (Vth>0).

For stacked PMOS transistors it's no pb. anyway, they just need their own nwells (which are connected to the respective source).

EPI wafers use a very low-resistive substrate with a thin epitaxially grown layer on it, of the same doping type, but with higher resistivity. This is the actual (NMOS) substrate. Because of the additional EPI process, they are bit more expensive than non-EPI wafers, but offer better EMI and noise isolation between different (guard-ringed) blocks.
 
Yes. For the bunch of flying NMOS transistors where sources are not connected to gnd you could use native NFETs (Vth≈0). As they are stacked at positions higher than gnd, they can easily be closed down (OFF), and also don't need much more gate control voltage for the ON state than their normal NFET brothers (Vth>0).

Great! you made my day! So, would you advise how to layout the native NMOS transistor? Also, in the schematic view is there a way to specify them instead of normal NMOS?
Can these native transistor withstand with 5V voltages or they are weak? (I just assumed the weakness form the name 'native')

For stacked PMOS transistors it's no pb. anyway, they just need their own nwells (which are connected to the respective source).

So you mean add nwells is different than ntap?

EPI wafers use a very low-resistive substrate with a thin epitaxially grown layer on it, of the same doping type, but with higher resistivity. This is the actual (NMOS) substrate. Because of the additional EPI process, they are bit more expensive than non-EPI wafers, but offer better EMI and noise isolation between different (guard-ringed) blocks.

OK, it's clear now. Actually, the technology I'm using is offered with EPI option, strangely they wrote for non-EPI option you need to pay more. anyway, I got it for this one and no need to bother :)
 

... would you advise how to layout the native NMOS transistor? Also, in the schematic view is there a way to specify them instead of normal NMOS?
Can these native transistor withstand with 5V voltages or they are weak?
If C5 has an option for native NMOSFETs, they will offer an extra schematic view for them, as well as simulation, and (pCell) layout and abstract views. May be native NMOSFETs are limited to larger min. W & L bounds than the normal NMOSFETs. If 5V native NMOSFETs are available, you should find out from your PDK description. I've never seen such.


So you mean add nwells is different than ntap?
For each flying PMOSFET you need an extra n-well. In this n-well you connect its ntaps (n+ diffusion in n-well) to the PMOSFET's source, so you get Vsb=0. That's it!


... strangely they wrote for non-EPI option you need to pay more.
I guess EPI wafers are standard nowadays. Standard is high volume, by that may be cheaper.
 
If C5 has an option for native NMOSFETs, they will offer an extra schematic view for them, as well as simulation, and (pCell) layout and abstract views. May be native NMOSFETs are limited to larger min. W & L bounds than the normal NMOSFETs. If 5V native NMOSFETs are available, you should find out from your PDK description. I've never seen such.

I went through most of documents I have for this technology but found nothing. I sent an inquiry to MOSIS with this regard.

Based on your experience, do think Transmission Gate (nMOS+pMOS) switch would be better option for flying switches? So, if native nMOS not supported, TG can work better than normal nMOS? I have not done deep analysis for my design if I use TG but I think it's worth looking.

For each flying PMOSFET you need an extra n-well. In this n-well you connect its ntaps (n+ diffusion in n-well) to the PMOSFET's source, so you get Vsb=0. That's it!

Yes, I just did that and it works!
 

... do think Transmission Gate (nMOS+pMOS) switch would be better option for flying switches? So, if native nMOS not supported, TG can work better than normal nMOS?

If you need an nMOS only - or a TG - depends on your application, i.e. voltage level(s) to be transferred. Possibly, a single nMOS or pMOS is enough. Source & load impedance and the necessary timing determine the needed W & L values. Under certain conditions, countermeasures against charge injection are necessary.

For "flying" switches not necessarily native nMOS are needed - again this depends on voltage levels to be switched, and if your control voltage range is adequate for this.
 
For "flying" switches not necessarily native nMOS are needed - again this depends on voltage levels to be switched, and if your control voltage range is adequate for this.

My circuit is intended to be self-powered from low voltage. First stage is to amplify a 500mV to 1V that can operates my logic gates and comparators (the whole control circuit). Then, this control circuit is driving the flying switches, so I am having about 1V rail-rail for control voltage range. When I did end-end transistor level simulation, it seems to be working fine. However, I always connect the Bulk to SOurces terminals. Then, I realized it is not always the case in C5 technology.

So, accounting for body effect will require higher voltage (close to 2V based on my calculation) which is something difficult to get. I like the option of native nMOS so I can take rid of the body effect.
 

I like the option of native nMOS so I can take rid of the body effect.

By using native nMOS you cannot get rid of the body effect. You just profit by their low threshold voltage Vt of about 0..200mV .

To close a switch (ON state) or a simple TG, the control voltage must be at least Vt higher (NMOS) or lower (PMOS) than the highest (lowest) voltage level to be transferred.
 
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