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RE: via spacing in Layout

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kenambo

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RE: via spacing in Layout

HI,

Why there are always spacing between vias ? What will happen if we use single big via?

Thanks
 

Re: via spacing in Layout

Well, it sounds like you are talking about GROUND vias between two ground planes on different layers. Many separated vias are used to keep the impedance as low as possible and to break up large loops into many smaller, less significant loops. For every ground connection, you will want as short a distance from the system ground as possible. If you were to use only one large via, the distance from system ground would go up, possibly causing problems, even though the total copper connecting the ground layers would be the same. Also, the could now be many large ground loops the could also cause a problem.
 

Re: via spacing in Layout

HI,

Why there are always spacing between vias ? What will happen if we use single big via?

Thanks

vias are holes, you can't make 2 holes next to each other as they would 'collapse'. that's the simplest answer. you can have redundant vias, via arrays, via bars, and other things. depends for what purpose.
 

Re: via spacing in Layout

It totally depends on DFM rules of your process...there is no such generic rule for VIAS
 

Re: via spacing in Layout

"Back in the day" I used many processes that laid down
only minimum via dimension rules and let vias be any
larger size (in fact 5-mil bond pads were built with single
full extent vias).

But smaller vias require more "tuning" to get repeatable
lithography and one common approach if to make a single
fixed size to optimize the process, against.

Another issue, depending on the via filling scheme, can
be the availability of fill material and the effects of a
limited "resource" on fill quality, step coverage and so
on. Consider a large "bed" of small vias (X>=3, Y>=3).
If the fill requires material flow (like hot metal dep, no
plug) then each via must pull its fill from not just
overhead, but adjacent deposited film. The ones on
the bed-edge see an expanse of clear field on one
or possibly two sides to draw from and will fill well.
Ones in the interior are going to fight over the small
amount between them and their neighbors, which
can leave them with a material deficit and cause
things like worse step coverage (degrading the
current capacity and series of resistance of the
large via construct, which is large presumably for
cause) or via voids which can be a reliability and
(in some markets) inspection yield risk.

In such cases I have seen large-bed via spacing
rules which are greater than doublet and 2x2 rules.
"Lonely" vias have the extra metal-metal space to
help them out, litho-wise.
 

Re: via spacing in Layout

vias are holes, you can't make 2 holes next to each other as they would 'collapse'. that's the simplest answer. you can have redundant vias, via arrays, via bars, and other things. depends for what purpose.

Hi,

Yeah they are holes and connection between two metals or poly. I am asking why in layout we have so much vias? We can easily connect metal1 and metal2 or 3 as a whole one right? Still we are connecting metal1 and 2 through number of vias? Is there any specific reason.

Thanks.

- - - Updated - - -

Well, it sounds like you are talking about GROUND vias between two ground planes on different layers. Many separated vias are used to keep the impedance as low as possible and to break up large loops into many smaller, less significant loops. For every ground connection, you will want as short a distance from the system ground as possible. If you were to use only one large via, the distance from system ground would go up, possibly causing problems, even though the total copper connecting the ground layers would be the same. Also, the could now be many large ground loops the could also cause a problem.
No, I concerned about layout. like metal to metal via or metal to poly via.
 

Re: via spacing in Layout

Hi,

It is a good idea to give related documents/pictures/infos, then we can discuss about it.

Is there any specific reason.
* current capability
* low impedance - especially with HF
* low thermal resistance

--> it depends on the application

Klaus
 

Re: via spacing in Layout

I can't understand what you are asking. try googling redundant vias, maybe that is what you are after.
 

Re: via spacing in Layout

Hi all,

I think this post has the answer for my question. https://www.edaboard.com/threads/95934/
In this post, They say large Via cause more stress so we split vias as small holes. Is that right?

Thanks
 

Re: via spacing in Layout

Via are connections between two layers (two tracks on different layers).

If you have a signal being carried between the layers, you are not much worried about power or current- you just want a good decent connection. In such cases, one or two vias may be sufficient. You sometimes use more than one to increase reliability.

If you are carrying power, you may like to use more via to carry larger current. They are now working in parallel and the current capacity will certainly increase with more vias. For ground planes, you want to reduce impedance and use more of them.

Sometimes we use via to carry heat from one side to other. Then we use as many as possible. You will find them under the PCB heat sinks!

In general, two small vias are better than one big one.
 

Re: via spacing in Layout

Perhaps you should be clear about whether you are talking
"PCB world" or "chip world", in all of this. The concerns have
different bases.

PCB vias are often "eyelet" style and conduction only
happens in the sidewall. More, smaller vias maximize the
useful periphery and throw away the not-useful via
internal area.
 

Re: via spacing in Layout

Perhaps you should be clear about whether you are talking "PCB world" or "chip world"

Oh, I see. The original poster was not clear enough or I was confused- as usual. These two beasts are of completely different breed.
 

Re: via spacing in Layout

Gentlemen, this is forum "Analog Integrated Circuit (IC) Design, Layout and Fabrication"
 

Re: via spacing in Layout

Yes, it is, hence my semiconductor focused remarks.
But I've seen some that look PCB-y and so brought
it up for clarity.
 

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