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27th August 2017, 18:04 #1
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VHDL Testbench getting (U) in simulation waveform result
Hi,
I'm trying to simulate 2bit full adder but getting U(undefined) in the waveform result. Can you help me with that please?
1bit full adder
Code:entity full_adder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; S : out STD_LOGIC; Cout : out STD_LOGIC); end full_adder; architecture Behavioral of full_adder is begin S<=A xor B xor Cin; Cout<=(A and B)or(B and Cin)or(A and Cin); end Behavioral;
Code:entity full_adder_2bit is Port ( A : in STD_LOGIC_VECTOR (1 downto 0); B : in STD_LOGIC_VECTOR (1 downto 0); Cin : in STD_LOGIC; S : out STD_LOGIC_VECTOR (1 downto 0); Cout : out STD_LOGIC); end full_adder_2bit; architecture Behavioral of full_adder_2bit is Component full_adder port(A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; S : out STD_LOGIC; Cout : out STD_LOGIC); end component; signal C:STD_LOGIC; begin Bit_adder0: full_adder port map(A=>A(0), B=>B(0), Cin=>Cin, S=>S(0), Cout=>C); Bit_adder1:full_adder port map(A=>A(1), B=>B(1), Cin=>C, S=>S(1), Cout=>Cout); end Behavioral;
Code:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity full_adder_2bit_tb is  Port ( ); end full_adder_2bit_tb; architecture Behavioral of full_adder_2bit_tb is component full_adder_2bit port( A : in STD_LOGIC_VECTOR (1 downto 0); B : in STD_LOGIC_VECTOR (1 downto 0); Cin : in STD_LOGIC; S : out STD_LOGIC_VECTOR (1 downto 0); Cout : out STD_LOGIC); end component; constant Period: Time :=10ns; signal A_tb: STD_LOGIC_VECTOR(1 downto 0):= (others=>'0'); signal B_tb:STD_LOGIC_VECTOR(1 downto 0):= (others => '0'); signal Cin_tb:STD_LOGIC; signal S_tb: STD_LOGIC_VECTOR(1 downto 0); signal Cout_tb:STD_LOGIC; begin Bit_adder_tb0: full_adder_2bit port map (A=>A_tb,B=>B_tb,Cin=>Cin_tb,S=>S_tb,Cout=>Cout_tb); stim_proc: process variable i,j :integer; begin for Cin in 0 to 1 loop for i in 0 to 2 loop for j in 0 to 2 loop A_tb <=STD_LOGIC_VECTOR( to_unsigned(i,2)); B_tb <= STD_LOGIC_VECTOR(to_unsigned(j,2)); wait for period; end loop end loop end loop wait; end process; end Behavioral;

27th August 2017, 18:04

27th August 2017, 18:45 #2
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Re: VHDL Testbench getting (U) in simulation waveform result
Cin isn't assigned in the test bench, hence will force u into the adder

27th August 2017, 18:45

28th August 2017, 02:57 #3
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Re: VHDL Testbench getting (U) in simulation waveform result
I've added the Cin value in the testbench but still getting the same issue with U in the whole waveforms simulation. How can I correct the code to get normal unsigned values in the waveform?
I'm also confused regarding using the STD_LOGIC and unsigned data type? is this related to the issue I'm facing?
The other query is that according to my understanding this code ,Code:signal Cin_tb:STD_LOGIC:='0';
Code:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity full_adder_2bit_tb is  Port ( ); end full_adder_2bit_tb; architecture Behavioral of full_adder_2bit_tb is component full_adder_2bit port( A : in STD_LOGIC_VECTOR (1 downto 0); B : in STD_LOGIC_VECTOR (1 downto 0); Cin : in STD_LOGIC; S : out STD_LOGIC_VECTOR (1 downto 0); Cout : out STD_LOGIC); end component; constant Period: Time :=10ns; signal A_tb: STD_LOGIC_VECTOR(1 downto 0):= (others=>'0'); signal B_tb:STD_LOGIC_VECTOR(1 downto 0):= (others => '0'); signal Cin_tb:STD_LOGIC:='0'; signal S_tb: STD_LOGIC_VECTOR(1 downto 0); signal Cout_tb:STD_LOGIC; begin Bit_adder_tb0: full_adder_2bit port map (A=>A_tb,B=>B_tb,Cin=>Cin_tb,S=>S_tb,Cout=>Cout_tb); stim_proc: process variable i,j :integer; begin for C in 0 to 1 loop Cin_tb<=STD_LOGIC(to_unsigned(C,1)); for i in 0 to 2 loop for j in 0 to 2 loop A_tb <=STD_LOGIC_VECTOR( to_unsigned(i,2)); B_tb <= STD_LOGIC_VECTOR(to_unsigned(j,2)); wait for period; end loop end loop end loop wait; end process; end Behavioral;

28th August 2017, 02:57

28th August 2017, 09:35 #4
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Re: VHDL Testbench getting (U) in simulation waveform result
Your loops are pretty useless as you are assigning 2 to both a and b. You are also assigning 1 to c, but this is in a syntax error. A stdlogic is a single bit, while an unsigned is an array of stdlogic that represents an unsigned number. You cannot convert am integer to single bit as it does not represent a number.
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