Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] ORing even & odd bits of a vector

Status
Not open for further replies.
rahdirs

rahdirs

Advanced Member level 1
Joined
May 22, 2013
Messages
424
Helped
93
Reputation
192
Reaction score
91
Trophy points
1,308
Location
Mordor
Activity points
4,492
Suppose, I have a vector:

Code Verilog - [expand]
1

logic [127:0] x; // one hot


I want to OR the even bits & odd bits seperately, as in x_even = x[0] | x[2] | x[4] | ...... x[126] & similarly for the odd bits. I tried the following but it's pointing a syntax error at |=
Code Verilog - [expand]
1
2
3
4
5
6

generate
  for (i=0;i<64;i++) begin
    x_even |= x[2*i];
    x_odd  |= x[2*i+1];
  end
endgenerate


Regards,
rahdirs
 

Code: 
  odd = |((64){2'b01} & x);
  even  = |((64){2'b10} & x);

I'm not sure if Verilog supports |=. SystemVerilog does.

In either case, this probably can't be done in a generate due to multiple assignments to the same net.
 
  • Like
Reactions: rahdirs

    rahdirs

    rahdirs

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top