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26th August 2017, 00:11 #1
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ORing even & odd bits of a vector
Suppose, I have a vector:
[syntax=verilog]logic [127:0] x; // one hot
[/syntax]
I want to OR the even bits & odd bits seperately, as in x_even = x[0]  x[2]  x[4]  ...... x[126] & similarly for the odd bits. I tried the following but it's pointing a syntax error at =
[syntax=verilog]generate
for (i=0;i<64;i++) begin
x_even = x[2*i];
x_odd = x[2*i+1];
end
endgenerate[/syntax]
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rahdirsIf I helped you, press the 'Helped Me' button.
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26th August 2017, 00:11

26th August 2017, 03:39 #2
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Re: ORing even & odd bits of a vector
Code:odd = ((64){2'b01} & x); even = ((64){2'b10} & x);
In either case, this probably can't be done in a generate due to multiple assignments to the same net.
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