+ Post New Thread
Results 1 to 4 of 4
  1. #1
    Newbie level 5
    Points: 996, Level: 7

    Join Date
    Jul 2012
    Posts
    10
    Helped
    0 / 0
    Points
    996
    Level
    7

    How to design self checking testbench...

    How can design self checking testbench for simple 2 input logic gates .....

    •   Alt22nd August 2017, 13:10

      advertising

        
       

  2. #2
    Advanced Member level 3
    Points: 4,490, Level: 15

    Join Date
    Apr 2016
    Posts
    939
    Helped
    173 / 173
    Points
    4,490
    Level
    15

    Re: How to design self checking testbench...

    do you understand what a self checking testbench IS?
    Really, I am not Sam.



    •   Alt22nd August 2017, 14:14

      advertising

        
       

  3. #3
    Full Member level 3
    Points: 1,399, Level: 8

    Join Date
    May 2014
    Posts
    160
    Helped
    18 / 18
    Points
    1,399
    Level
    8

    Re: How to design self checking testbench...

    #2 What's your understanding of a self-checking test bench?

    #1 Consider the following
    simple 2 input logic gates

    If we have A OR B = ?
    We can have a conditional statement that says
    ? = 1 when A = '1' OR B = '1' , but not when they are both '0'.

    Therefore you have a comparative check based on what you know it should be vs what your uut is outputting.
    You can use commands like (vhdl) assert to check and report an output to the console.

    For a more robust testbench you really want to be outputting to a text file with test number and test pass/fail state.



    •   Alt23rd August 2017, 11:04

      advertising

        
       

  4. #4
    Newbie level 3
    Points: 196, Level: 2

    Join Date
    Nov 2016
    Posts
    4
    Helped
    8 / 8
    Points
    196
    Level
    2

    Re: How to design self checking testbench...

    Self-checking can be done in testbench. You can write a kind of the same behavior code(correct results should be) in testbench and compare the self-checking results in testbench with the data from the code under test. Then, report the comparison results during simulation. You can refer to this as an example testbench: http://www.fpga4student.com/2017/01/...fo-memory.html . In this code, I added the self-checking code in the testbench. After writing to the FIFO, I started reading data from FIFO and compare with the data from self-checking code. Then, display the comparison results during simulation.


    2 members found this post helpful.

--[[ ]]--