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  1. #1
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    Use two separate codes in FPGA

    Hello!

    I am working on interfacing the ADC and the DAC of a Spartan-3A starter kit. I have written a code for the ADC interface and DAC interface separately. I wanted to know how I can use these two separate codes together? Can I program the FPGA with more than one bit file?

    If so, how can I get the data from ADC to DAC? Or send data from FPGA to DAC to test my code?

    Thanks in advance.

    •   Alt21st August 2017, 10:47

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    Re: Use two separate codes in FPGA

    Hi,

    I don´t know if you have made both projects with VHDL, verilog, schematic....
    --> But the simple answer is: merge both projects to get one complete project.

    You can´t load more than one bit file into an FPGA.

    Klaus



    •   Alt21st August 2017, 11:59

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  3. #3
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    Re: Use two separate codes in FPGA

    Quote Originally Posted by KlausST View Post
    You can´t load more than one bit file into an FPGA.
    Klaus
    Technically this is not true. You can use partial reconfiguration to load different partial configuration images into an initial base configuration image.



    •   Alt21st August 2017, 16:12

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    Re: Use two separate codes in FPGA

    Hi,

    Wow. I´ve never heard about that. Is this possible with XILINX´Spartan 7 and Spartan 3?
    I need to do an internet search..

    Klaus



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    Re: Use two separate codes in FPGA

    I'm not sure if it is available with Spartan 3/7, I've only used it on Kintex 7 and Virtex 7. It's a separate license and it is rather hard to even get the part number for a purchase request. I suspect Xilinx doesn't promote it much because it is an advance flow which typically requires an excessive amount of user support. From what I've heard it's mostly used by those in the government contract space. Formerly it was very very difficult to work with, in Vivado it's pretty easy to use.

    So if it is even available in Spartan 3 I would avoid it. As Spartan 7 is in Vivado there is a chance it will be supported.



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    Re: Use two separate codes in FPGA

    partial reconfiguration was the buzzword some 7-5 years ago. it seems the industry has kind of moved on from that. it made a lot of sense for space applications, but not so much for other domains.
    Really, I am not Sam.



    •   Alt22nd August 2017, 14:17

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  7. #7
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    Re: Use two separate codes in FPGA

    Hahaha partial configuration.
    Open vivado 2017.x, open your project, tools>enable partial reconfiguration (software crashes)
    https://forums.xilinx.com/t5/Vivado-...he/td-p/765522

    However from what I'm reading of #1. It sounds like you just need to have a toplevel that includes your two interfaces. Rather than having separate bitfiles


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    Re: Use two separate codes in FPGA

    Yes, the OP's problem is not solved by PR. It is only the follow up conversation about using "two bit files" that is relevant.



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