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synthesys in synopsys design compiler

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abhishek7

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Hi am using synopsys design compiler for synthesizing my design and using the netlist in VCS simulation and am getting warning as,suppose i use a reg[10:0] and am assigning to a signal B[5:0] during synthesis the remaining bits are considering as dontcares by the synthesys tool and functionality of the design gets differed so how do i prevent this? is there any constraints for this?can you please help me out am very new to this...


thanks
Abhishek
 

Using multiple simple sentences with proper punctuation will help to explain the problem better.

suppose i use a reg[10:0] and am assigning to a signal B[5:0] during synthesis the remaining bits are considering as dontcares by the synthesys tool and functionality of the design gets differed so how do i prevent this?
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The 5 bits are unused so DC will try to optimize them away. What is the optimization_effort you have selected? Try it with minimum and see what happens.

Is this dropping of 5 bits by design? How is the 11 bits register loaded/populated?
In any case you should ask the RTL design engineer as to why this is done (did that person make a mistake?).
 

if you design 11 but only use 6, naturally the tool will drop all the unnecessary bits. it's dead logic. just make sure to design using sizes and bitwidths that match.
 

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