abhishek7
Newbie level 3
Hi am using synopsys design compiler for synthesizing my design and using the netlist in VCS simulation and am getting warning as,suppose i use a reg[10:0] and am assigning to a signal B[5:0] during synthesis the remaining bits are considering as dontcares by the synthesys tool and functionality of the design gets differed so how do i prevent this? is there any constraints for this?can you please help me out am very new to this...
thanks
Abhishek
thanks
Abhishek