Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Load Capacitance Calculation

Status
Not open for further replies.

samster19

Newbie
Joined
May 15, 2017
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
73
Hi, I am building a control amplifier for a VCO. The output voltage of the amplifier will drive a sensing PMOS and a charging PMOS (in the VCO)of 6*12u/1 and 3*15/1.5 each. To compute the load capacitance on the amplifier, I ran a dc on the oscillator to find out the Cgs+Cgd+Cgb of the PMOS's, (input capacitance), but I am not sure I had the right answer because of the sign conventions. Instead, I tied the gates of similar sized PMOS's at the output of the amplifier and shorted the respective drain and source. I am still not sure if I am doing the right thing.

Then I guesstimated the input capacitance of the VCO to be 1pF. Do I have the right values? Please help, thanks!
 

... The output voltage of the amplifier will drive a sensing PMOS and a charging PMOS (in the VCO)of 6*12u/1 and 3*15/1.5 each. To compute the load capacitance on the amplifier, I ran a dc on the oscillator to find out the Cgs+Cgd+Cgb of the PMOS's, (input capacitance), but I am not sure I had the right answer because of the sign conventions.

The simplest way to find the total capacitance c at an individual node is to inject a unit ac current into this node and measure the resulting voltage. Connect an idc current source with AC Magnitude=1 via a huge cap (e.g. 1F) between GND and the node to be measured. Then run either an ac or an xf analysis over an appropriate frequency sweep range. Both analyses use a linearized model, hence the value of the current doesn't matter; a unit current value (1A) results in a voltage value which corresponds directly to an impedance (Ω) value at this node; kV -> kΩ.

For the ac analysis, plot the node's voltage vs. frequency. Note the low frequency value of this voltage (resp. impedance) Z0, where the capacitive effect isn't yet involved. Then note the frequency f, where the voltage (resp. impedance) has decreased to the 1/√2 - fold (or -3dB) of the low frequency value. At this frequency f, the capacitive node reactance (the imaginary part of the impedance) has the same value as the low frequency resistance (the real part of the impedance) Z0 (remember: real & imaginary values are added quadratically). Hence c = 1/sf*Z0 = 1/(2πf*Z0) .

After an xf analysis, from the ADE menu select Results -> Direct Plot -> Main Form ... In the Direct Plot Form menu, choose the Function Transimpedance, then either Magnitude, Phase or dB20 (with Imaginary I had no success). You'll be asked to Select Current Source on schematic... Click the current source and you'll get the appropriate curve. The 1/√2 , the -45° or the -3dB points should give you the same frequency f as from the ac analysis.

This is a standard method to analyse the total cap from an individual node to GND (also possible between 2 different nodes).
 

Connect an idc current source with AC Magnitude=1 via a huge cap (e.g. 1F) between GND and the node to be measured.

Just one small question: As I understood, you mean to connect the cap in series with the current source, why?
 

Just one small question: As I understood, you mean to connect the cap in series with the current source, why?

In order to not make a short circuit for the DC bias at this node.
Perhaps it's not necessary: I'm not sure if the idc source has an infinite impedance for DC, too?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top