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High Level employment of the "imply" operator

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BrownBear1968

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Almost all of the 16 possible logic 2-variable operations can be exemplified with some kind of what I will call here as a medium/high-level circuit.

Example:
A XOR gate can be presented with half/full-adders.
ANDs, ORs, NOTs, NANDS, NORs with its several applications (mux, demux, encoders/decoders, etc).

But I couldn´t find an example for the imply operation A --> B (or A' + B)

A B A->B
0 0 1
0 1 1
1 0 0
1 1 1


Does anybody know any kind of medium-high level example wich uses the imply operator?
Regards
 

I'm not sure I understand your question; it looks like you already have your answer:

Out=(NOT A) OR B.

This would be an OR gate with B on one input and a NOT gate on the other input; the input to the NOT is A.
 

I'm not sure I understand your question; it looks like you already have your answer:

Out=(NOT A) OR B.

This would be an OR gate with B on one input and a NOT gate on the other input; the input to the NOT is A.

Hi berry,

thank you for your reply.

Yes, the imply operator produces the same effect as the A' + B.

What I am looking for is any combinational circuit that regularly employs the "imply as an imply operator".
An example: we usually prefer to express A XOR B instead of A'B + AB'.


Regards
 

I don't understand the exact problem. You know how to implement the intended logic operation, as a matter of fact an "imply" operator isn't available in most commonly used logic description languages.

Seriously, I don't even see it's purpose.
 

Hi berry,

thank you for your reply.

Yes, the imply operator produces the same effect as the A' + B.

What I am looking for is any combinational circuit that regularly employs the "imply as an imply operator".
An example: we usually prefer to express A XOR B instead of A'B + AB'.


Regards

I am so lost. Are you talking about expression factoring?
 

I suspect the OP is asking about basic logic circuits that are normally drawn using different types of gates.

For example, xor is used in the conditional invert, full-adder, and parity. xnor for compare equal. "and" for enable.

I'm not familiar of any circuit that performs a basic function that uses this operation. There are certainly complex circuits that have this logic.

I guess CPU pipelines can allow this logic. allow_pipeline_progress = (data_ready implies sink_ready); If data_ready is true and sink_ready is false the pipeline stalls. if data_ready is false the value might not matter.
 

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