sanjaysharmaiitk
Member level 1
i am using calibre with innovus (encounter) .
i am geting problem in LVS
WARNING: XDB Database not available: No comparison was made
Comparison result :some are ERROR coming "port name not valid for netlisting "
Extraction result : some are WARNING coming "Power net missing in layout. Ground net missing in layout"
how to solve these problem.
i am doing LVS for UART verilog code.
comparing spice netlist file generated from verilog file using script " l2vs" command in calibre
Note:
v2lvs -v uart_mnet.v -o uart_NOmnet.cdl -l /cad/cadence/TechLib/SCL/scl_pdk/stdlib/fs120/verilog/vcs_sim_model/tsl18fs120_scl.v -s /cad/cadence/TechLib/SCL/scl_pdk/stdlib/fs120/cdl/tsl18fs120_scl_no_supply_pins.cdl -sk -s0 VSS -s1 VDD
and compare with .gds file generated after merge cell .gds file available in pdk and .map file available in pdk.
i am geting problem in LVS
WARNING: XDB Database not available: No comparison was made
Comparison result :some are ERROR coming "port name not valid for netlisting "
Extraction result : some are WARNING coming "Power net missing in layout. Ground net missing in layout"
how to solve these problem.
i am doing LVS for UART verilog code.
comparing spice netlist file generated from verilog file using script " l2vs" command in calibre
Note:
v2lvs -v uart_mnet.v -o uart_NOmnet.cdl -l /cad/cadence/TechLib/SCL/scl_pdk/stdlib/fs120/verilog/vcs_sim_model/tsl18fs120_scl.v -s /cad/cadence/TechLib/SCL/scl_pdk/stdlib/fs120/cdl/tsl18fs120_scl_no_supply_pins.cdl -sk -s0 VSS -s1 VDD
and compare with .gds file generated after merge cell .gds file available in pdk and .map file available in pdk.