Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

difference between cdl and sp file.

Status
Not open for further replies.

sanjaysharmaiitk

Member level 1
Joined
Jul 28, 2017
Messages
33
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Location
KANPUR
Activity points
280
i am using calibre with innovus (encounter) .
i am geting problem in LVS
WARNING: XDB Database not available: No comparison was made

Comparison result :some are ERROR coming "port name not valid for netlisting W1.png"
Extraction result : some are WARNING coming "Power net missing in layout. Ground net missing in layout"COMPARIZON.png

how to solve these problem.
i am doing LVS for UART verilog code.
comparing spice netlist file generated from verilog file using script " l2vs" command in calibre

Note:
v2lvs -v uart_mnet.v -o uart_NOmnet.cdl -l /cad/cadence/TechLib/SCL/scl_pdk/stdlib/fs120/verilog/vcs_sim_model/tsl18fs120_scl.v -s /cad/cadence/TechLib/SCL/scl_pdk/stdlib/fs120/cdl/tsl18fs120_scl_no_supply_pins.cdl -sk -s0 VSS -s1 VDD

and compare with .gds file generated after merge cell .gds file available in pdk and .map file available in pdk.
 

i am using calibre with innovus (encounter) .
i am geting problem in LVS
WARNING: XDB Database not available: No comparison was made

Comparison result :some are ERROR coming "port name not valid for netlisting View attachment 140605"
Extraction result : some are WARNING coming "Power net missing in layout. Ground net missing in layout"View attachment 140606

how to solve these problem.
i am doing LVS for UART verilog code.
comparing spice netlist file generated from verilog file using script " l2vs" command in calibre

Note:
v2lvs -v uart_mnet.v -o uart_NOmnet.cdl -l /cad/cadence/TechLib/SCL/scl_pdk/stdlib/fs120/verilog/vcs_sim_model/tsl18fs120_scl.v -s /cad/cadence/TechLib/SCL/scl_pdk/stdlib/fs120/cdl/tsl18fs120_scl_no_supply_pins.cdl -sk -s0 VSS -s1 VDD

and compare with .gds file generated after merge cell .gds file available in pdk and .map file available in pdk.

just make sure your gate level netlist has power ports for all gates
 
layout verification

just make sure your gate level netlist has power ports for all gates

i used DC(Design compiler) for synthesis
after synthesis get-level netlist has been generated.
i have attached gate-level netlist of a small design
johnson counter.
i gat-level netlist no power port are defined.
how to define power port in verilog gate-level netlist ?

Note:
in layout i used rings for suppy "vdd" and "gnd".
 

Attachments

  • V.png
    V.png
    119 KB · Views: 116

Re: layout verification

i used DC(Design compiler) for synthesis
after synthesis get-level netlist has been generated.
i have attached gate-level netlist of a small design
johnson counter.
i gat-level netlist no power port are defined.
how to define power port in verilog gate-level netlist ?

Note:
in layout i used rings for suppy "vdd" and "gnd".

your standard cell library provider probably has another version of the library that has power pins. use that version instead.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top