[SOLVED] Does a post layout (calibre / hspice) sim reveal unintended forward biased diode

Dear All,

Recently, we encountered an issue in one of our chips where someone accidentally connected a psub guard ring to VDD instead of GND. Post chip tapeout we noticed heavy leakage current whenever input voltage was given to the pad in which the guard ring was connected with the opposite polarity. Schematic wise the pad works just fine. I am wondering if a post-layout sim (using calibre or hspice) can reveal this unintended diode and the associated heavy leakage current ? Otherwise we have no way of catching these errors. Note that the chip was DRC/LVS clean.

Thanks in anticipation.

Yes.

Post layout extractions should include Rs, Cs and any potential diodes not covered by LVS. Ideally, guard ring diodes should be found by LVS to prevent an issue like the one you are having.

rangermad said:

Ideally, guard ring diodes should be found by LVS to prevent an issue like the one you are having.

Click to expand...

Right. In nkp6195's case, the extraction rules should find the guard ring diodes (intrinsically: all diodes). If not, I'd think the extraction rules' set is not complete!

nkp6195 said:

Note that the chip was DRC/LVS clean.

Click to expand...

This, not the layout extracted simulation, is where I'd
be pointing the finger and swinging the bat. Because
as you say there was a miswiring and yet your layout
verification failed to catch it.

Either the instance(s) involving the psub guardring
had the same bad connection in the schematic, or the
schematic and layout did not in fact match. There ought
to have been a vdd-vss short chip-wide in the LVS results.

If the schematic carries the psub connection error (as
wire net property or as instance B terminal property,
as the case may be for the PDK in question) then a
schematic based simulation should show the diode lit
up. Presuming that the parasitic diodes are properly
modeled in the FET model subcircuit or compact model,
which is not to be assumed especially on non-I/O or
"digital" devices. This same model chain presumably
would be applied to an extracted view based simulation.

So one test would be to simulate a single NMOS device
in the application, with body attached to vdd potential.
You see either a ton of excess source current (!= drain)
or not. That tells you about general validity of D-B, S-B
diode model features implementation.

But I'd push into why you believe that LVS was clean
when you know there was a wiring fault in fact.

Thank you for your responses !

As you correctly pointed out, LVS was, infact not completely clean. LVS passed with stamping conflicts and ERC did not pass. I ran LVS again and verified the ERC error: 'ptap connected to VDD'