Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

ECSM characterization

Status
Not open for further replies.

viviadam

Newbie level 4
Joined
Aug 8, 2017
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
80
What does ECSM capacitance mean? Why do we set separate threshold point when determining the ECSM capacitance at pin level and timing level?
The format for pin level is:
Code:
Pin A
{
    ...
    ...
    ecsm capacitance (rise) {
    threshold_pct =50.0
     index1=(...)
     values=(...) 
     }
     ...
     ...
}

for timing arc level:
    //
    ....
    rise_transition()
     {
           waveform_1 {}
           waveform_'n'  {}
           ecsm_capacitance (rise)
           {
               threshold_pct = 50.0
               ...
              }     
           ecsm_capacitance (rise)
           {
               threshold_pct = 70.0
               ...
              }     
          }
What does threshold_pct mean and why we set seperate threshold points to sweep the capacitances?
Thank you,
 
Last edited by a moderator:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top