nkp6195
Newbie level 4
Dear All,
I am designing a circuit for dc stress characterization of an array of transistors. I have two voltage domains in this circuit sharing a common ground (Stress Voltage and Nominal Voltage). The stress voltage comes from a bare pad whereas nominal voltages are esd protected. Testing involves dc stress application for long hours and simple Id-Vg tests thereafter.
As any careful designer, I have added maximum possible body taps / vias.
Now my first question is, do I need a guard ring for this circuit, given that I need to occasionally (every ~5 min or so) switch the nominal VDD digital circuit and there is no switching in the stress vdd domain ?
Would a N-Well tie ring (connected to stress Vdd) and psub tie ring (connected to GND) placed between the two vdd domains be helpful in preventing any kind of latch-up that might happen ? (Note that these are well ties, not guard rings)
Do I really need a guard ring / well tie at all, given that the node is 65nm and everything is dc (I will design PCB with a lot of LC filters so hopefully all high frequency noise is filtered out)
Thanks in anticipation.
I am designing a circuit for dc stress characterization of an array of transistors. I have two voltage domains in this circuit sharing a common ground (Stress Voltage and Nominal Voltage). The stress voltage comes from a bare pad whereas nominal voltages are esd protected. Testing involves dc stress application for long hours and simple Id-Vg tests thereafter.
As any careful designer, I have added maximum possible body taps / vias.
Now my first question is, do I need a guard ring for this circuit, given that I need to occasionally (every ~5 min or so) switch the nominal VDD digital circuit and there is no switching in the stress vdd domain ?
Would a N-Well tie ring (connected to stress Vdd) and psub tie ring (connected to GND) placed between the two vdd domains be helpful in preventing any kind of latch-up that might happen ? (Note that these are well ties, not guard rings)
Do I really need a guard ring / well tie at all, given that the node is 65nm and everything is dc (I will design PCB with a lot of LC filters so hopefully all high frequency noise is filtered out)
Thanks in anticipation.