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[Moved]: Guard Ring / Well Tie for a dc test circuit

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nkp6195

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Dear All,

I am designing a circuit for dc stress characterization of an array of transistors. I have two voltage domains in this circuit sharing a common ground (Stress Voltage and Nominal Voltage). The stress voltage comes from a bare pad whereas nominal voltages are esd protected. Testing involves dc stress application for long hours and simple Id-Vg tests thereafter.

As any careful designer, I have added maximum possible body taps / vias.

Now my first question is, do I need a guard ring for this circuit, given that I need to occasionally (every ~5 min or so) switch the nominal VDD digital circuit and there is no switching in the stress vdd domain ?

Would a N-Well tie ring (connected to stress Vdd) and psub tie ring (connected to GND) placed between the two vdd domains be helpful in preventing any kind of latch-up that might happen ? (Note that these are well ties, not guard rings)

Do I really need a guard ring / well tie at all, given that the node is 65nm and everything is dc (I will design PCB with a lot of LC filters so hopefully all high frequency noise is filtered out)

Thanks in anticipation.
 

Re: Guard Ring / Well Tie for a dc test circuit

The guardrings are for ESD / latchup current path
control. If you are confident that your handling and
test is benign then you may decide to accept the
remaining risk. Though this is not really quantifiable
except in retrospect.

On the other hand I'm in favor of "test it like you fly
it" and like test structures to either represent what
is going to be used, or represent the corners of that
device-space. If normal layout would have no core
region guardrings then I'd omit them from the test
array - on the chance that it -will- fail for cause,
and then you'd know.

Because a passing test result on a conservative
layout that doesn't match eventual applications,
is only a false sense of security.
 
Re: Guard Ring / Well Tie for a dc test circuit

Thanks for the response !

Still looking for answers to qs 2 and 3. Just to clarify, although the core transistors have no guard rings, as you correctly pointed out, the purpose of putting a single guard ring at the intersection of the two VDD domains is with regards to the safety of the stress circuit itself. Would a well tie ring work the same way too ?
 

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