bio_man
Full Member level 2
Hi,
For IC layout in general, I know we need fingering when we have large W compared to L to get compact layout and to decrease gate resistance.
for my case, I have a 300kHz clocked comparator with differential pairs nmos of 7.2um/0.6um. Do you think I need fingering here?
I thought no need for that for couple of reasons:
1) W is around 12 times L. not too wide. (I'm assuming W=10L is acceptable without fingering)
2) switching frequency is not high, so I shouldn't pay attention to RF issues.
3) I have enough room to fit these transistors without fingering.
my questions:
Am I thinking in the right way? or always we need to do fingering for differential pair?
second, Are guard rings around the differential pair important in this comparator layout?
Lastly, Do you think 0.6um gate length is ok for comparators? I run the spectre simulation and had no issues. but I want to see if this is good or not based on your experience.
For IC layout in general, I know we need fingering when we have large W compared to L to get compact layout and to decrease gate resistance.
for my case, I have a 300kHz clocked comparator with differential pairs nmos of 7.2um/0.6um. Do you think I need fingering here?
I thought no need for that for couple of reasons:
1) W is around 12 times L. not too wide. (I'm assuming W=10L is acceptable without fingering)
2) switching frequency is not high, so I shouldn't pay attention to RF issues.
3) I have enough room to fit these transistors without fingering.
my questions:
Am I thinking in the right way? or always we need to do fingering for differential pair?
second, Are guard rings around the differential pair important in this comparator layout?
Lastly, Do you think 0.6um gate length is ok for comparators? I run the spectre simulation and had no issues. but I want to see if this is good or not based on your experience.