Gate fingering in clocked comparators

Hi,

For IC layout in general, I know we need fingering when we have large W compared to L to get compact layout and to decrease gate resistance.

for my case, I have a 300kHz clocked comparator with differential pairs nmos of 7.2um/0.6um. Do you think I need fingering here?
I thought no need for that for couple of reasons:
1) W is around 12 times L. not too wide. (I'm assuming W=10L is acceptable without fingering)
2) switching frequency is not high, so I shouldn't pay attention to RF issues.
3) I have enough room to fit these transistors without fingering.

my questions:
Am I thinking in the right way? or always we need to do fingering for differential pair?
second, Are guard rings around the differential pair important in this comparator layout?
Lastly, Do you think 0.6um gate length is ok for comparators? I run the spectre simulation and had no issues. but I want to see if this is good or not based on your experience.

Going to more fingers probably buys you only a little -
nf=2, drain at center, cuts the drain bottom plate
area in half and periphery by maybe 1/3 (depends
on the L-direction extent of the D region).

If you do this to switches then you might worry a
bit about charge asymmetry (2S, 1D != 1S, 1D).
A clocked comparator cares a lot about switching
charge as the primary offset term (presumably this
comparator is nulled and "snaps to" on clock edge,
carrying the charge asymmetry, if any, forward).

I've built a 5V (higher actually) 0.6u SOI comparator
that worked OK. You might find there are some areas
that benefit from longer (like if this has a style that
is an inverter string with shorting switches, Idd is
going to be more variable and higher during the null
phase when channels are short; do you need the
minimum L everywhere?

dick_freebird said:

If you do this to switches then you might worry a
bit about charge asymmetry (2S, 1D != 1S, 1D).
A clocked comparator cares a lot about switching
charge as the primary offset term (presumably this
comparator is nulled and "snaps to" on clock edge,
carrying the charge asymmetry, if any, forward).

Click to expand...

I see. So, you usually suggest to have odd number of fingers which will make sure that I have the same number of D and S?

what do you think of W=10L rule of thumb ( I heard it somewhere), is it acceptable to not finger the MOSFET if it has W=10L or close?

I've built a 5V (higher actually) 0.6u SOI comparator
that worked OK. You might find there are some areas
that benefit from longer (like if this has a style that
is an inverter string with shorting switches, Idd is
going to be more variable and higher during the null
phase when channels are short; do you need the
minimum L everywhere?

Click to expand...

yes, I used the minimum L everywhere (logic gates and differential pair and later in my power transistor for main circuit. Because I am expecting there is no channel length nonlinearity in the 600nm gate length, righ?