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Suggestion on methodology/ways to test internal logic analyzer softcore modules

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promach

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Using https://zipcpu.com/blog/2017/06/08/simple-scope.html , I have rewritten my internal logic analyzer at https://github.com/promach/internal_logic_analyzer

Could anyone suggest methodology/ways to test my softcore modules ?

Screenshot from 2017-08-14 11-58-48.png
 

Could anyone suggest methodology/ways to test my softcore modules ?
Click to expand...

You may know that Xilinx provides ILA core for free to be used as internal scopes. Is it not possible to use your own scope (in a place where an ILA core has already been used and the results have been recorded) and compare its behavior with ILA?
 

Should I use traditional memory testing algorithms such as March algorithm or Walking 1/0 ?
 

I can't answer that I don't know. My answer was at a very superficial level.
You have a known-system and you know its behavior(ILA core). You design a system similar to the known-system. So plug out the working system, put in your own-system and observe its behavior. I didn't look into into you RTL nor do I know in-depth how Xilinx ILA core works.
So I might be wrong in my suggestion.
 


I am stuck at testing my internal scope.

**broken link removed**

raddr does not start increment at the right time...

already checked my read_enable logic, seems correct

Screenshot from 2017-08-24 16-00-48.png
 

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