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    Suggestion on methodology/ways to test internal logic analyzer softcore modules

    Using http://zipcpu.com/blog/2017/06/08/simple-scope.html , I have rewritten my internal logic analyzer at https://github.com/promach/internal_logic_analyzer

    Could anyone suggest methodology/ways to test my softcore modules ?

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    •   Alt14th August 2017, 05:03

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    Re: Suggestion on methodology/ways to test internal logic analyzer softcore modules

    Could anyone suggest methodology/ways to test my softcore modules ?
    You may know that Xilinx provides ILA core for free to be used as internal scopes. Is it not possible to use your own scope (in a place where an ILA core has already been used and the results have been recorded) and compare its behavior with ILA?
    .....yes, I do this for fun!



    •   Alt14th August 2017, 10:23

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    Re: Suggestion on methodology/ways to test internal logic analyzer softcore modules

    Should I use traditional memory testing algorithms such as March algorithm or Walking 1/0 ?



    •   Alt14th August 2017, 13:45

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    Re: Suggestion on methodology/ways to test internal logic analyzer softcore modules

    I can't answer that I don't know. My answer was at a very superficial level.
    You have a known-system and you know its behavior(ILA core). You design a system similar to the known-system. So plug out the working system, put in your own-system and observe its behavior. I didn't look into into you RTL nor do I know in-depth how Xilinx ILA core works.
    So I might be wrong in my suggestion.
    .....yes, I do this for fun!



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    Re: Suggestion on methodology/ways to test internal logic analyzer softcore modules

    When we test the scope within our bench/cpp Verilator testbench, we'll know if our test was "correct" if the counter 1) only ever counts by 1, and 2) if test was "correct" if the counter 1) only ever counts by 1, and 2) if the trigger lands on thte right data sample.
    What does it mean by the above code comments and https://github.com/ZipCPU/wbscope/bl...scope_tb.v#L73 ?



    •   Alt14th August 2017, 16:09

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    Re: Suggestion on methodology/ways to test internal logic analyzer softcore modules

    I am stuck at testing my internal scope.

    https://github.com/promach/internal_...read_mem.v#L19

    raddr does not start increment at the right time...

    already checked my read_enable logic, seems correct

    Click image for larger version. 

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