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HV clock translation

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filip.amator

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Hello!

I am looking for idea how to convert clock with unusual levels into something like 3.3V/2.5V TTL. The low level of the clock might be between 0 and 2.5V and high level is expected to be from 10V to 12V. Clock frequency is around 4 MHz, but the rise time of the edges should be at reasonable level to interface it with FPGA. I found nice chip from Linear LTC1045 but it's availability in EU is limited. I could use comparator like ADCMP371/ADCMP370 with HV input but propagation time is huge. Another idea is to use an ordinary voltage divider from 0603 resistors and fast comparator like AD8611. Do you have any other ideas how to do it?
 

I think using a resistive divider with a fast comparator is a good way to go.

Keep the resistor values to no more than a few kΩ to minimize delays from stray capacitance.
 

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