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  1. #1
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    Instantiated my custom logic in vivado axi full slave (supports burst) template.

    Hello all,

    I created a axi slave full template in vivado and instantiated my custom logic into it and working fine but the problem is , i cant assign a value to my register "value_given" and cant able to read it back.

    please observe the code.

    Code:
    /// assume axi template here ///
    //user logic starts
    my_ip uut
    (
    .rst(!s00_axi_restn),
    .max_value(max_value),
    .x(x),
    .y(y),
    .z(z)                                            //assume this is the only output
    );
    
    always@(s00_axi_aclk)
    if(axi_aresetn)
    max_value <= 'h10;
    else if(my_valid)
    max_value <=  value_given;
    
    always@(s00_axi_aclk)
    if(axi_aresetn)
        value_given <= 0;
    else if(awren && S_AXI_WSTRB)
         begin
             if(S_AXI_AWADDR = 20'h10004) begin
               value_given <= S_AXI_WDATA;
               my_valid <= 1'b1;
                 end
         end
    
    assign axi_rdata <= (S00_AXI_ARADDR == 20'h10004) ? value_given : z; //here z case (false case)working fine and verified burst transfers also in sdk
    assign S00_AXI_RDATA <=  axi_rdata;
    
    //user logic ends
    the problem here is, upon reset "max_value" becomes 10 and the custom logic is working fine and verified on SDK. but i am unable to give new value into this address 20'h10004 and even cant retrieve the value what i assign into this address . i checked mwr 0xc00010004 30 and did (mrd 0xc00010004 5 ) returns all zero's.

    please help where im going wrong.

    •   Alt11th August 2017, 19:44

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  2. #2
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    Re: Instantiated my custom logic in vivado axi full slave (supports burst) template.

    You don't know the AXI protocol. You are mixing the address and data phases of the transaction. You should read the Xilinx AXI document. You should be modifying the template not just adding random logic that doesn't follow the protocol to the file.



    •   Alt12th August 2017, 00:58

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  3. #3
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    Re: Instantiated my custom logic in vivado axi full slave (supports burst) template.

    Quote Originally Posted by ads-ee View Post
    You don't know the AXI protocol. You are mixing the address and data phases of the transaction. You should read the Xilinx AXI document. You should be modifying the template not just adding random logic that doesn't follow the protocol to the file.
    I am not modifying the template i just replaced the example byte_ram memory block provided in the template. I am trying to write into my own single 32-bit register and read it back. but somewhere going wrong.



    •   Alt12th August 2017, 07:04

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  4. #4
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    Re: Instantiated my custom logic in vivado axi full slave (supports burst) template.

    Selectively reading my post...

    I'll say it again you are not following AXI4 protocol and are using the AXI signals incorrectly mixing and using the wrong signals to complete the transfer.

    Read the AXI spec, you obviouly have not done that before using the protocol.



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    Re: Instantiated my custom logic in vivado axi full slave (supports burst) template.

    I also think the verilog code is broken, so you might be facing multiple problems here. the non-blocking assign is so weird.
    Really, I am not Sam.



    •   Alt12th August 2017, 18:37

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  6. #6
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    Re: Instantiated my custom logic in vivado axi full slave (supports burst) template.

    Quote Originally Posted by ThisIsNotSam View Post
    I also think the verilog code is broken, so you might be facing multiple problems here. the non-blocking assign is so weird.
    chi chi. it always happens with me while typing here. Anyhow i figured it out and fixed it and i had my own memory block with a configurable memory size works fully with axi. but this template not working for 128-bit data_width size.



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