gzantass
Newbie level 3
Hi guys
I was working on RTL compiler with my code. and I got this module.
As you can see there is an 24 bit output Z, and the last 3 bit of Z are assigned to 1'b0;
later, when the top module called this submodule,
here is the code:
and you can see the last 3 bits are not connected to net.
So in the netlist, these 3 bits are not doing anything.
How did the RTL compiler synthesis them out, why not just use a 21 bit output instead?
And most important question, how should i fix this problem please？
Thanks
I was working on RTL compiler with my code. and I got this module.
As you can see there is an 24 bit output Z, and the last 3 bit of Z are assigned to 1'b0;
Code:
module mult_unsigned_const_184(A, Z);
input [15:0] A;
output [23:0] Z;
wire [15:0] A;
wire [23:0] Z;
wire n_0, n_1, n_2, n_4, n_5, n_6, n_7, n_8;
wire n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16;
wire n_17, n_18, n_19, n_20, n_21, n_22, n_23, n_24;
wire n_25, n_27, n_28, n_29, n_30, n_31, n_32, n_33;
wire n_34, n_35, n_36, n_37, n_38, n_39, n_40, n_41;
wire n_42, n_43, n_45, n_46, n_47, n_48, n_49, n_50;
wire n_51, n_52, n_53, n_54, n_55, n_56, n_57, n_58;
wire n_59, n_60, n_61, n_63, n_65, n_67, n_69, n_71;
wire n_73, n_75, n_77, n_79, n_81, n_83, n_85, n_87;
wire n_89, n_91;
assign Z[0] = 1'b0;
assign Z[1] = 1'b0;
assign Z[2] = 1'b0;later, when the top module called this submodule,
here is the code:
Code:
mult_unsigned_const_184 const_mul_158_28(.A ({data_0[15:11], n_1414,
data_0[9:7], n_1856, data_0[5], n_1451, n_1578, data_0[2:0]}),
.Z ({n_3927, n_3926, n_3925, n_3924, n_3923, n_3922, n_3921,
n_3920, n_3919, n_3918, n_3917, n_3916, n_3915, n_3914, n_3913,
n_3912, n_3911, n_3910, n_3909, n_3908, n_3907, UNCONNECTED14,
UNCONNECTED15, UNCONNECTED16}));and you can see the last 3 bits are not connected to net.
So in the netlist, these 3 bits are not doing anything.
How did the RTL compiler synthesis them out, why not just use a 21 bit output instead?
And most important question, how should i fix this problem please？
Thanks
