beginner_EDA
Full Member level 4
Hi,
I am using following reference design for 12G-SDI:
https://www.xilinx.com/support/docu...e-sdi-interfaces-7series-gtx-transceivers.pdf
It is mentioned in its known issue that CDR setting is default and not optimal for 12G-SDI and thus occasionally RX CRC error occurs. I have same problem as indicated by its flags(see attachment with red marker)
Is anybody already worked with 12G-SDI? I would like to know what is the optimized CDR settings for 12G-SDI? Where I can get this info?
P.S. CDR -> Clock and data recovery.
I am using following reference design for 12G-SDI:
https://www.xilinx.com/support/docu...e-sdi-interfaces-7series-gtx-transceivers.pdf
It is mentioned in its known issue that CDR setting is default and not optimal for 12G-SDI and thus occasionally RX CRC error occurs. I have same problem as indicated by its flags(see attachment with red marker)
Is anybody already worked with 12G-SDI? I would like to know what is the optimized CDR settings for 12G-SDI? Where I can get this info?
P.S. CDR -> Clock and data recovery.