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optimized CDR settings for 12G-SDI

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beginner_EDA

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Hi,
I am using following reference design for 12G-SDI:
https://www.xilinx.com/support/docu...e-sdi-interfaces-7series-gtx-transceivers.pdf

It is mentioned in its known issue that CDR setting is default and not optimal for 12G-SDI and thus occasionally RX CRC error occurs. I have same problem as indicated by its flags(see attachment with red marker)

Is anybody already worked with 12G-SDI? I would like to know what is the optimized CDR settings for 12G-SDI? Where I can get this info?


P.S. CDR -> Clock and data recovery.
 

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  • error_12g.jpg
    error_12g.jpg
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If you are using the RX equalizer in DFE mode, please try the LPM mode.
If there is too little randomness in the data, there can be spurious errors in the DFE mode. 8b/10b coding does not guarantee enough randomness.

Also look at "Choosing Between LPM and DFE Modes" in the data sheet.
 

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