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  1. #1
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    Cannot Read Data in 1-Port RAM IP Core

    Hi all.
    I am using a 1-port RAM created using Altera Quarus 16 Lite(IP Catalog). It has width of 16 bits and depth of 64 words. I store in data from a computing register in it and want to read it after some time as I will use this data as input for another module. The data transmission is fine but as I make write_enable '0' and read_enable '1', I receive only first and last data bytes(and middle 1-62 data is lost). But If I make write_enable '1' and read_enable '1' its working fine with a delay of 1 cycle. I do not understand if I am really saving data in RAM or not. Here is behavioral code.Here is the link https://stackoverflow.com/questions/...rt-ram-ip-core to the original question as I cannot post the code and problem in here as it exceeds the allowed character length.
    Thanks in advance.
    Last edited by FvM; 10th August 2017 at 16:43. Reason: Moved to FPGA section

    •   Alt10th August 2017, 09:40

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  2. #2
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    Re: Cannot Read Data in 1-Port RAM IP Core

    First, this is in the wrong section of the forum. Second, your code is reading from address 0 at all times as pointed out in the stackoverflow thread.
    Really, I am not Sam.



    •   Alt10th August 2017, 15:35

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  3. #3
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    Re: Cannot Read Data in 1-Port RAM IP Core

    You use en as both a write enable and as a clock enable. Using rst1 as a control signal to reset the address is a poor design choice.

    Next time post the code on edaboard. Use code or syntax (preferred) tags. They are applied by placing the following tags around your code. Note remove all spaces (spaces added to keep the tags from taking effect).
    [ code ]
    -- your code goes here
    [/ code ]
    or
    [ syntax=vhdl ]
    -- your code goes here
    [/ syntax ]



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