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  1. #1
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    VHDL Instantiation in modelSim

    Hi i have written a vhdl code along with the testbench..when i simulate it in the modelSim i don't get an expected result

    The VHDL Code is given below

    Code VHDL - [expand]
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    Library ieee;
        use ieee.std_logic_1164.all;
        entity PowerSeq is
            port(fpga_clk: in std_logic; 
                    Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out std_logic;
                    PG_3V3: in std_logic);
        end PowerSeq;
        
        architecture MPU_PowerSeq of PowerSeq is 
        
            signal pon_state: integer:= 0;
        begin
        
            process(fpga_clk) 
            begin
                if(rising_edge(fpga_clk)) then
                
                    if(pon_state = 0) then
                        Enable_3V3 <= '1';
                        Enable_1P5V <= '1';
                        Enable_1V <= '0';
                        Enable_Bias_1V <= '1';
                        pon_state <= 1;
                    end if;
                        if(pon_state = 1) then
                            if(PG_3V3 = '1') then
                                Enable_1V <= '1';
                            end if;
                        end if;
                        
                    end if;
                end process;
        end MPU_PowerSeq;



    and the Test bench is also given below

    Code VHDL - [expand]
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    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.std_logic_unsigned.all;
    entity PowerSeq is
    end PowerSeq;
     
    architecture MPU_PowerSeq of PowerSeq is
     
    component Sequence is
        port(fpga_clk : in std_logic;
            Reset: in std_logic;  
                 Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out std_logic;
             PG_3V3: in std_logic);
        end component;
     
    signal  Reset: std_logic:= '0';
    signal  fpga_clk : std_logic:= '0';
    signal  Enable_Bias_1V: std_logic:= '0';
    signal  Enable_3V3: std_logic:= '0';
    signal  Enable_1P5V: std_logic:= '0';
    signal  Enable_1V: std_logic:= '0';
    signal  pon_state: integer:= 0;
    signal PG_3V3: std_logic:= '0';
    constant tb_time: time:= 15.5 ns;
     
    begin
    uut: sequence port map(
        Reset => Reset,
        fpga_clk => fpga_clk,
        Enable_Bias_1V => Enable_Bias_1V,
        Enable_3V3 => Enable_3V3,
        Enable_1P5V => Enable_1P5V,
        Enable_1V => Enable_1V,
        PG_3V3 => PG_3V3
        ); 
     
    stimlus: process
    begin
        fpga_clk <= '0' after tb_time, '1' after 2 * tb_time;
        wait for 2 * tb_time;
    end process;
     
    tb: process
    begin
    wait for 50 ns ;
    Reset <= '0';
    Enable_Bias_1V <= '0';
    Enable_3V3 <= '0';
    Enable_3V3 <= '0';
    Enable_1V <= '0';
    wait for 50 ns;
    Reset <= '1';
    wait for 1 us;
    end process;
     
    end;




    Click image for larger version. 

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  2. #2
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    Re: VHDL Instantiation in modelSim

    What exactly are you expecting to see? the UUT is clearly not the same as the code you posted - it is a different named entity (PowerSeq in code, Sequence in testbench) and it has a different port map (PowerSeq has no reset port).

    So, why not post the code thats actually being simulated?



  3. #3
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    Re: VHDL Instantiation in modelSim

    Quote Originally Posted by TrickyDicky View Post
    What exactly are you expecting to see? the UUT is clearly not the same as the code you posted - it is a different named entity (PowerSeq in code, Sequence in testbench) and it has a different port map (PowerSeq has no reset port).

    So, why not post the code thats actually being simulated?
    the below is the code which i compiled in modelsim. but when i start simulation it is showing error in loading design

    Code VHDL - [expand]
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    Library ieee;
        use ieee.std_logic_1164.all;
        entity PowerSeq is
            port(fpga_clk,Reset: in std_logic; 
                    Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out std_logic;
                    PG_3V3, PG_1V: in std_logic);
        end PowerSeq;
        
        architecture MPU_PowerSeq of PowerSeq is 
        
            signal pon_state: integer:= 0;
        begin
        
            process(fpga_clk)
            begin
                if(rising_edge(fpga_clk)) then
                
                if(reset = '1') then
                    Enable_3V3 <= '0';
                    Enable_1P5V <= '0';
                    Enable_1V <= '0';
                    Enable_Bias_1V <= '0';
                end if;
                if(pon_state = 0) then
                    Enable_3V3 <= '1';
                    Enable_1P5V <= '1';
                    Enable_1V <= '0';
                    Enable_Bias_1V <= '1';
                    pon_state <= 1;
                end if;
                    if(pon_state = 1) then
                        if(PG_3V3 = '1') then
                            Enable_1V <= '1';
                        end if;
                    end if;
                    
                    end if;
                end process;
        end MPU_PowerSeq;

    test bench is given below

    Code Verilog - [expand]
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    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.std_logic_unsigned.all;
    entity PowerSeq is
    end PowerSeq;
    architecture MPU_PowerSeq of PowerSeq is
    component PowerSeq is
        port(fpga_clk      : in std_logic;
               Reset         : in std_logic;  
           Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out std_logic;
             PG_3V3        : in std_logic
             );
        end component;
        
        signal   Reset          : std_logic:= '0';
        signal   fpga_clk       : std_logic:= '0';
        signal   Enable_Bias_1V : std_logic:= '0';
        signal    Enable_3V3     : std_logic:= '0';
        signal   Enable_1P5V    : std_logic:= '0';
        signal    Enable_1V      : std_logic:= '0';
        signal   pon_state      : integer:= 0;
        signal   PG_3V3         : std_logic:= '0';
        constant tb_time        : time:= 1 ns;
    begin
     --sim:/powerseq 
    uut: PowerSeq port map(
        Reset => Reset,
        fpga_clk => fpga_clk,
        Enable_Bias_1V => Enable_Bias_1V,
        Enable_3V3 => Enable_3V3,
        Enable_1P5V => Enable_1P5V,
        Enable_1V => Enable_1V,
        PG_3V3 => PG_3V3
        ); 
        
    stimlus: process
    begin
        fpga_clk <= '0' after tb_time, '1' after  2 * tb_time;
        wait for 2 * tb_time;
    end process;
     
    tb: process
        begin
        wait for 5 ns ;
        Reset <= '0';
        Enable_Bias_1V <= '1';
        Enable_3V3 <= '1';
        Enable_1P5V <= '1';
        wait for 5 ns;
        if(pon_state = 0) then
        Enable_Bias_1V <= '1';
        Enable_3V3 <= '1';
        Enable_1P5V <= '1';
        pon_state <= 1;
        end if;
        if(pon_state = 1) then
        PG_3V3 <= '1';
        Enable_1v <= '1';
        end if;
        -- wait for 5 ns;
        --Reset <= '1';
        end process;
     
    end;



    •   Alt10th August 2017, 10:00

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  4. #4
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    Re: VHDL Instantiation in modelSim

    Im surprised you got this to work, as your testbench has the same entity name as the UUT.
    You also seem to be driving outputs from the UUT in the testbench, so I dont beleive the wave form you shows is from simulating any code you have posted.
    Please find out exactly what you are simulating, and post it.



  5. #5
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    Re: VHDL Instantiation in modelSim

    Quote Originally Posted by TrickyDicky View Post
    Im surprised you got this to work, as your testbench has the same entity name as the UUT.
    You also seem to be driving outputs from the UUT in the testbench, so I dont beleive the wave form you shows is from simulating any code you have posted.
    Please find out exactly what you are simulating, and post it.
    Code

    Code VHDL - [expand]
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    library ieee;
    use ieee.std_logic_1164.all;
    entity powering is 
        port(fpga_clk,Reset: in std_logic;
            Enable_Bias_1V, Enable_3V3, Enable_1P5V, Enable_1V: out std_logic;
            PG_3V3, PG_1V: in std_logic);
    end powering;
    architecture behavioral of powering is
    signal pon_state : integer := 0;
    begin
    process(fpga_clk) 
    begin
    if(rising_edge(fpga_clk)) then
    if(pon_state=0) then
    Enable_3V3 <= '1';
    Enable_1P5V <= '1';
    Enable_Bias_1V <= '1';
    pon_state <= 1;
    end if;
    if(pon_state = 1) then
        if(PG_3V3 = '1') then
        Enable_1V <= '1';
        end if;
    end if;
    end if;
    end process;
    end behavioral;



    Testbench

    Code VHDL - [expand]
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    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.std_logic_unsigned.all;
    entity sequence is
    end sequence;
    architecture behav of sequence is 
    component powering port(
        Reset: in std_logic:= '0';
        fpga_clk : in std_logic:= '0';
        Enable_3V3 : out std_logic:= '0';
        Enable_1p5V: out std_logic:= '0';
        Enable_1V: out std_logic:= '0';
        Enable_Bias_1V : out std_logic:= '0';
        PG_3V3: in std_logic:= '0');
    end component;
     
    signal  Reset: std_logic:= '0';
    signal  fpga_clk : std_logic:= '0';
    signal  Enable_Bias_1V: std_logic:= '0';
    signal  Enable_3V3: std_logic:= '0';
    signal  Enable_1P5V: std_logic:= '0';
    signal  Enable_1V: std_logic:= '0';
    signal  pon_state: integer:= 0;
    signal PG_3V3: std_logic:= '0';
    constant tb_time: time:= 1 ns;
    begin
    uut: powering port map (
            Reset => Reset,
        fpga_clk => fpga_clk,
        Enable_Bias_1V => Enable_Bias_1V,
        Enable_3V3 => Enable_3V3,
        Enable_1P5V => Enable_1P5V,
        Enable_1V => Enable_1V,
        PG_3V3 => PG_3V3
        ); 
    stimuls: process
    begin
        fpga_clk <= '0' after tb_time, '1' after 2 * tb_time;
        wait for 2 * tb_time;
    end process;
     
    tb: process
    begin
        wait for 5 ns;
        Reset <= '1';
        Enable_Bias_1V <= '0';
        Enable_3V3 <= '0';
        Enable_1P5V <= '0';
        Enable_1V <= '0';
        Enable_Bias_1V <= '0';
        wait for 5 ns;
        PG_3V3 <= '1';
        Enable_1V <= '1';
    end process;
    end;



  6. #6
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    Re: VHDL Instantiation in modelSim

    Im sorry, this STILL isnt the correct code. The component does not match the entity.
    So I suggest this is a massive user error.



  7. #7
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    Re: VHDL Instantiation in modelSim

    The uut is powering which is the entity name of main code. the same should be assigned to the component right?
    And i could even compile this code in modelsim without any error..but i couldnt do the simulation.



    •   Alt10th August 2017, 11:42

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  8. #8
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    Re: VHDL Instantiation in modelSim

    The latest code you posted in post #5 has a missmatch between the "powering" entity and "powering" component. the entity has a port called PG_1V and the component does not, so you cannot map the component to the entity (you get a compile/mapping error).

    So what you have posted clearly is NOT what you have tried to simulate or compiled, as it will not compile for me.
    The fact you have posted 3 different sets of code that ALL have this problem, I suspect your project is a bit of a mess. Please tidy it up.



  9. #9
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    Re: VHDL Instantiation in modelSim

    Quote Originally Posted by TrickyDicky View Post
    The latest code you posted in post #5 has a missmatch between the "powering" entity and "powering" component. the entity has a port called PG_1V and the component does not, so you cannot map the component to the entity (you get a compile/mapping error).

    So what you have posted clearly is NOT what you have tried to simulate or compiled, as it will not compile for me.
    The fact you have posted 3 different sets of code that ALL have this problem, I suspect your project is a bit of a mess. Please tidy it up.
    IS there any issue other than this PG_1V?



  10. #10
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    Re: VHDL Instantiation in modelSim

    Quote Originally Posted by hareeshP View Post
    IS there any issue other than this PG_1V?
    Yes, you are driving the outputs of the UUT, so you will get X's in the testbench if the UUT drives '0' and the TB drives '1' (or vice versa)
    Why are you driving the outputs of the UUT from the testbench?



  11. #11
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    Re: VHDL Instantiation in modelSim

    Quote Originally Posted by TrickyDicky View Post
    Yes, you are driving the outputs of the UUT, so you will get X's in the testbench if the UUT drives '0' and the TB drives '1' (or vice versa)
    Why are you driving the outputs of the UUT from the testbench?
    Actually in the main code if the pon_state is 0, signals Enable_3V3, Enable_1p5V and Enable_Bias_1V should be activated. If the pon_state is 1, PG_3V3 is monitored, if it is '1' Enable_1V is activated. But i could not find a way to implement this in test bench thats is why im driving outputs UUT in tb. And is it okay to use 'if' statement inside component instantiation?
    Last edited by hareeshP; 10th August 2017 at 13:40.



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    Re: VHDL Instantiation in modelSim

    you post shows you still have a total lack of understand of VHDL - I highly suggest finding a digital logic textbook and actually reading it.


    1 members found this post helpful.

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    Re: VHDL Instantiation in modelSim

    can you suggest best book to learn vhdl?



    •   Alt10th August 2017, 13:52

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  14. #14
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    Re: VHDL Instantiation in modelSim

    This often comes out as a good book:
    https://www.fpgarelated.com/books/31.php



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    Re: VHDL Instantiation in modelSim

    I think they have a lack of understanding of digital design. The code presented does not implement a circuit that would likely work as the power enables would be constantly "on" all the time. As there isn't even a default for the 1V enable it might not even power up as 0.

    Makes me wonder if these power enables go to the POL supplies for the FPGA that is enabling them...

    A power sequencer is typically implemented as a FSM not this ad hoc 32-bit integer pon_state, there is no power down sequence to shut off the power (which usually requires power to be removed in the opposite order of power on). There is no "protection" from rails not being up before the 1V is enabled or is 3.3V the only rail required for 1V to be up?



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