bio_man
Full Member level 2
Hi,
I'm beginner to Cadence and for testing, I layout a simple inverter using 0.5um CN05 technology. After extraction, LVS reported a matched layout with schematic.
Now, I want to run post-layout simulation. My questions:
1) How can I run ADE simulator (I'm using Spectre) with the extracted layout?
2) How can I extract the parasitics? Can I see the parasitic capacitance value and how?
3) Can I link the symbol to the extracted layout not the schematic? because I want to make sure that I am running a post layout simulation all the time.
I appreciate your input.
I'm beginner to Cadence and for testing, I layout a simple inverter using 0.5um CN05 technology. After extraction, LVS reported a matched layout with schematic.
Now, I want to run post-layout simulation. My questions:
1) How can I run ADE simulator (I'm using Spectre) with the extracted layout?
2) How can I extract the parasitics? Can I see the parasitic capacitance value and how?
3) Can I link the symbol to the extracted layout not the schematic? because I want to make sure that I am running a post layout simulation all the time.
I appreciate your input.