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Determine Technology Current using foundry models

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deveshkm

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I am studying the below mentioned paper for determining the technology current.

Reference : https://www.semanticscholar.org/pap...Roth/e62f5fc47bb158f09db3eb652f15e00be60c0d72

L = 2u W = 2u
Technology Current I0

These are the steps I followed :
1. Plot id vs vgs (with vds =1.8 and vgs swept from 0 to 700m)

2. Plot gmoverid using below methods
a) Add gmoverid from function in Cadence Virtuoso
b) Used derivative function (deriv(i("/M0/D" ?result "dc")) / i("/M0/D" ?result "dc"))

They give different results

3) Used the formula to determine SQL
log10(ID/ I0)**-0.5) * MAX(gmoverId)

4) Plot gm/Id (2a and 2b) and SQL versus Id

5) Expressions in ADE-L
For min distance between the SQL and maximum gmbyid

Delta_Y = abs(ymin((SQL - gmoverid)))

ISSUES

a. From the reference paper, I have deduced that the transistor must be kept in saturation.
Please do comment on the circuit diagram used for this.

b. I have used multiple iterations for estimating I0 , till 50uA .
But, Delta_Y is around 22.
I need to minimize this to ensure that the technology current , I0 is accurate.

c. In Cadence Virtuoso Visualization and Analysis XL (graphs), I am unable to add tangent function to the plot obtained in step 4)

Please comment on the issues and suggest modifications to methods.
I would appreciate if you could provide some references schematic_techcurrent.jpg
 

2. Plot gmoverid using below methods
a) Add gmoverid from function in Cadence Virtuoso
b) Used derivative function deriv(i("/M0/D" ?result "dc")) / i("/M0/D" ?result "dc"))
They give different results
Are you sure that (deriv(i("/M0/D" ?result "dc")) is ID's derivative with respect to VGS ? (gm = ∂ID/∂VGS)

3) Used the formula to determine SQL
log10(ID/ I0)**-0.5) * MAX(gmoverId)
No: SQL = log10 {(ID/ I0)**-0.5 * MAX(gmoverId)}

...
ISSUES

a. From the reference paper, I have deduced that the transistor must be kept in saturation.
Please do comment on the circuit diagram used for this.
This is ok, because V0 = VDS > VGS


...
c. In Cadence Virtuoso Visualization and Analysis XL (graphs), I am unable to add tangent function to the plot obtained in step 4)
If you can't do it arithmetically (line with slope -1/2 through measured point), try it graphically.

...
I would appreciate if you could provide some references
You have provided above a very useful paper. Here is another one.
 

Thanks. I will make the changes in SQL equation.

Is it possible to estimate the technology current from the foundry?
 

Thanks.
The technology is SCL 180nm.
But, my design requires L_min = 500 nm.

From the plot obtained between g_m/ I_D and I_D/I_0 , I find that strong inversion slope (-1) is found at much lower value of IC .
Ideally it should occur at higher IC .
 


You should get a Technology Current value of a 180nm process, about 0.6 ... 1µA for NFETs.


No: -1/2 , s. here: View attachment 140448

Thanks for the reference.


Please find attached the results obtained for with the updated formula.

I observed that the SQL doesn't extend up to the point where the IC becomes 1.

I had swept Vgs till 1.8, before plotting Y vs Y for gmoverid vs Id.

Please comment on these results.
Thanks
 

techcurrent_I0_50u_gmoverid_vs_Id.jpg
No results to be found!

???

The SQLdoesn't extend upto the entire range of vgs. hence i am unable to get the difference, (Delta y) as shown in the paper.

PFA the results.

All results obtained are here: https://drive.google.com/open?id=0B2sp7Ex5C8mdakdhUTlVcDhQR0k

*****************************************************************************************************************************

In an alternative way I have referred to another paper on this by Willy Sansen
https://drive.google.com/open?id=0B2sp7Ex5C8mdZ181MktMTEI3SGo0ckc4ejZ2UDQyTVpXMDQw

Here , the relationship between the normalized voltage and drain current is used.

Based on the theoretical value of v for IC = 1 and IC = 0.01, a range of technology current is obtained.
I got values of 765nA and 910nA. But, I doubt whether this is correct approach.



techcurrent_I0_50u_gmoverid_vs_Id.jpg


Thanks for your time and effort.
 

Based on the theoretical value of v for IC = 1 and IC = 0.01, a range of technology current is obtained.
I got values of 765nA and 910nA. But, I doubt whether this is correct approach.

These values are good results for NFETs, s. Binkley's and my values above.
 
I am grateful to you, (erikl) for your response.

Reference 2 : https://drive.google.com/open?id=0B2sp7Ex5C8mdZ181MktMTEI3SGo0ckc4ejZ2UDQyTVpXMDQw

I used the v vs IC plot for determining tech current


Using 900nA and 950nA as the technology current, I started the designing common source amplifier with current source load.

specs : GBW = 1MHz Load Cap = 10pF Input DC voltage = 900mV output DC level = 900mV

This transconductance gm (nmos) = 62.8 uS.

From the gm vs IC plot , the value of IC obtained is 9.8.

In IC based method, choice of technology current strictly dictates the region of operation.
How can we afford inaccuracy?

Plotted gm vs Id with vgs =vds = 0.9V and W= L = 1um

I0 = 0.95uA
I chose (W/L) = Id/(9.8*0.95u)

But, when used these values in CS amplifier with current source load , I did not get the same value of gm for nmos.
From gm vs IC plot obtain gm for W= L =1 ,

Isn't it obvious that value of gm would change, as (W/L) will have to be varied to meet the Id requirements.

I will attach the obtained results soon.

Thanks for your time and effort!
 

...
In IC based method, choice of technology current strictly dictates the region of operation.

There's no choice of technology current: Technology current is a measurement result. Drain current and W/L ratio determine the region of operation!
 

Ok.

From the v vs IC, I obtained these results:
Id = 367nA at IC = 0.5
Id = 950nA at IC = 1

Hence, I decided to choose I0 around 900nA

From the gm vs IC plot , IC = 9.8

Now I have two choices:

a. Keep W/L = 1 to get required gm. This doesn't ensure that transistor is in saturation.
b. (W/L) = 3 and get more current . But this will reduce gm
 

... Now I have two choices:

a. Keep W/L = 1 to get required gm. This doesn't ensure that transistor is in saturation.
b. (W/L) = 3 and get more current . But this will reduce gm

I'm still not sure what you actually want: A certain gm? A certain Id? In which circuit?
 

Eventual Goal is to design Differential Difference Amplifier.

specs given in terms of gain, bandwidth and need to optimize the input referred noise.

Presently, I am learning the IC based design methodology.
So, I am designing a CS amplifier with GBW 1MHz , CM level = 900mV and Cl = 10pF.
So, I need to have gm around 62u. The transistor must stay in saturation(region =2 in Cadence Virtuoso)
As of now, this doesn't happen.

The results obtained for Io , by using extreme points, gives a range of 735-950nA.
So I tried to 'choose' Io in order to get the reqd gm in moderate inversion.

However, value of gm and region of transistor are different
 

I am designing a CS amplifier

I'd suggest you show your schematic as it is now. We don't know if it's still single input or already differential, resistor or transistor load, straight or folded cascode, NFET or PFET input, 1-stage or 2-stage, differential or single ended output? Which threshold voltages? Required gain?

The exact value of the technology currents (for N & PFETs) isn't so very important: it doesn't matter too much if it's 0.5 or 1µA, so don't put too much effort in getting a more exact value. I0n=0.9µA for 180nm NFETs is close enough. But you should find I0p for the PFETs too, of course.

For GBW=1MHz and Cl = 10pF you'll need a drain current of Id=10µA , so W/L=1 should be fine for the NFET(s).
 

For GBW=1MHz and Cl = 10pF you'll need a drain current of Id=10µA , so W/L=1 should be fine for the NFET(s).

Thinking twice, for such low GBW I guess you can get by with 1..2µA , but W/L ≫ 1 , operating in moderate inversion.

But then you trade power for silicon area consumption.
 

Designing a common source amplifier with current source load.
Obtained gm = 62uS at IC = 3.55 . This means drain current should be 3.4uA.

NMOS : vth = 425mV

From IC = 3.55 , v = 0.49
=> Vgs should be around 430mV.
Plotted I vs W and used W = 9.2u for Id= 3.4uA
obtained gm = 71u


**broken link removed**
It is calculated using formula for IC in moderate inversion

IC = [ln(ev +1) ]2

Do i need to calculate v?

I used the above formula.
calculated vgs from v and found W to obtain desired current

for PMOS current source I used following setup
vs = 1.8 V vg = 1.2 V vd = 0.9V

In the CS Amplifier I obtained the following results from ac analysis:
gain = 7dB
UGB = 1.047 MHz
PM = 63 degrees
 

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