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Missing instance discrepancy

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Vijay Vinay

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Hi all,
When I am trying to design my emitter follower layout design in Cadence Virtuoso 6.1, I am getting discrepancies like "Missing instance" for resistor "restan" in my layout design. However, I have used the same resistor which I have used for my schematic. Even all the parameters like resistance value, width, length are all the same. But, still I am receiving such discrepancies. I am not sure how to solve these issues. Could anyone help me to get rid of these discrepancies.FYI, I have attached the schematic, layout as well as the error windows along with this post.

Thanks

emiteter_follower.jpeg
layout_emitter_foll.jpeg
LVS_layout_ef.jpeg
 

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  • emitter_follower.jpeg
    emitter_follower.jpeg
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Your layout plot shows all instances as outlines. So it is
unclear whether the instance is not found, or just not
extracted properly.

Some PDKs require stuff like placement of a "bulk"
polygon in the layout before certain devices will get
extracted. You could read backward through the
extract deck to see the chain of logic and layers
that underpin extraction.
 

Did you compare schematic and extracted view?
 

Hi,
I am not sure, wjhat exactly you are saying. How to find the extracted view of my layout design
 

Hi,
I have checked the extracted view of my layout design, there aren't any errors available or atlease there isn't any description about my layout design. I don't know why , eventhough I have used the same resistors in my layout design,that I have used in my schematic design, I am getting errors during my LVS. Because of this, I am getting other descrepancies like missing net due to the missing resistance instances in my layout design. Please help me out to solve this issue.Thanks in advance.
 

Hard to tell with the info you have given. Increase your layout display depth so we can see all your layers. Also expand the nets and ports discrepancies.

Does your layout have a substrate tie to VSS?
 
Hi rangermad,
How to make a substrate tie to VSS?
 

Assuming a P type substrate: active, pimp, contact, metal. However, your PDK may have a specific layer to use instead of active for this purpose.
 

Hi rangermad,
I have a 'metal layer 5', the so called active layer, where I have connected the vee pin to it. Is it possible to connect VSS to this metal layer. Or how to connect VSS?
 

There's the layer which is active for drawing, and
there's "active" (active area, thinOx, ...) drawing
layer/purpose pair.

Your library may have a "ptap" cell, or a P+ contact
cell.

Pruning rules may eliminate devices which have less
than two connections. You need to view / edit the
extracted view and see if the devices are showing.

You connect signals by using (say) met5/pin with
the proper net name in the properties field. The
same layer as the interconnect feature, but "pin"
purpose. There is a create pin function in the same
general area of the menus as you use to create
instances (try 'p' bindkey, case / control variations)

All of the schematic pins should have a corresponding
layout pin.
 

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