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Regrading Pass transistor realization of reversible adder circuits

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shashi106

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Hello,

I am designing 4 bit carry sip adder using reversible logic using pass transistors in tanner s-edit v.15 0.25um technology at 2.5V. My results are correct for pass transistor realization of the individual reversible gates for all the input combinations but when I am going for 1 bit full adder and further some of the outputs are not correct with respective input combinations.Why this is so? I know that in pass transistors, output voltage levels are less than input voltage levels. But what can be done for obtaining correct outputs for all the input sets.
Please help me.

Thanking You
 

Too vague, can't help you without further details. Your netlist could be wrong, the number of pass transistors in series could be too high, your 'reversible logic' could be flawed, etc.
 

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