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  1. #1
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    FPGA timing due to Dist ram

    Hi all,
    I am working with prototyping.

    I am getting a lot of timing violation due to Ram getting inferred as 150 Dist rams. I made it block ram but still the issue is my design has asynch read and reads the data as soon as raddr gets updated, but Bram has got synch read and waits till next rising edge....

    So wat can be solution for this????

    •   Alt6th August 2017, 10:42

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  2. #2
    Advanced Member level 5
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    Re: FPGA timing due to Dist ram

    If your design has async read and writes, then it cannot be inferred as block ram - you will have to change the design.



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