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    xilinx ip core to calculate square root without cordic

    hi all,
    I am new to this forum and i am beginer in FPGA verilog designs. I need to calculate square root of a decimal number (ex:- 23.456) in zc702 board in efficient way than CORDIC ip core for my project. It is very kind of you if anyone can let me know about any ipcore or algorithms which can calculate square root of decimal number within 2 or 3 clock cycles. thank you.

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    Re: xilinx ip core to calculate square root without cordic

    Hi,

    What range are your decimal values? What resolution and what precision do you need?
    --> maybe it's possible to switch to binary numbers instead of decimal numbers.

    Btw: why decimal values inside an FPGA? Quite unusual.

    Klaus



    •   Alt5th August 2017, 19:16

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    Re: xilinx ip core to calculate square root without cordic

    Thank you for replying me. Sorry if my post is unclear. What my target is to have fixed point representation for decimal numbers.(18 bit for integer part and 14 bit for fractional part). What I want to perform is square root of number represented in 32 bits. It's okay to have precision up to 2 bit. Our project is about running vision algorithm and this is a part of it.



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    Re: xilinx ip core to calculate square root without cordic

    Hi,

    Then perfor the square root of the uint32.
    The result is uint16 with 9 integers and 7 fractional bits.

    Klaus


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    •   Alt6th August 2017, 20:45

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    Re: xilinx ip core to calculate square root without cordic

    Hi,
    Thank you Klaus. Is there a way to perform it without using CORDIC ip available in xilinx tools? Yes I know there are many research papers for that, but I am looking for special IP. Thank you for keep replying me.



    •   Alt7th August 2017, 07:10

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    Re: xilinx ip core to calculate square root without cordic

    Hi,

    I can't help you with existing IP.

    But you could code it on your own.
    I once build a very efficient and precise to 1LSB square root algorithm with 16 bit result for microcontrollers.
    It worked with a 256 item lookup table, if I remember right.

    Klaus


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    Re: xilinx ip core to calculate square root without cordic

    Hi,
    Thank you very much for your guidance Klaus. You did a great job for me.



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    Re: xilinx ip core to calculate square root without cordic

    hi,

    you can do it with restoring or non restoring algorithm. you need to code it
    It is very kind of you if anyone can let me know about any ipcore or algorithms which can calculate square root of decimal number within 2 or 3 clock cycles
    yes you can do it, but your working frequency will be low. you need to code it serially .there is one paper available in google. search for it please.

    regards


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    Re: xilinx ip core to calculate square root without cordic

    Hi,
    Thank you diplin for your reply. Can you tell me whether we can find square root within 2 or 3 clock cycles using restoring or non restoring algorithm?Is this the paper you mentioned.
    Name: New efficient hardware design methodology for modified non-restoring square root algorithm
    Authors: Atul Rahman, Abdullah-Al-Kafi
    Link: http://ieeexplore.ieee.org/document/...6/?reload=true

    In this paper it says it can be configured to calculate square root of 32 bit length number within 8 clock cycles( more than 2 or 3 clock cycles )

    Thank you very much for your guidance and it's very great if you can guide me more



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    Re: xilinx ip core to calculate square root without cordic

    I think you should refactor your design. Computer vision makes me think you have several pixels, channels, etc... If this is the case you can likely channelize the design where you make use of a pipeline and have multiple independent calculations in the pipeline. I am suspicious that you actually need low-latency vs high-bandwidth.



    •   Alt9th August 2017, 03:55

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    Re: xilinx ip core to calculate square root without cordic

    hi,
    Can you tell me whether we can find square root within 2 or 3 clock cycles using restoring or non restoring algorithm?
    if you pipeline your design, then you will have a initial latency of 16 clock cycles (may be 17 ) after that for every clock cycle you will get the out put. so the initial latency is allowed or not?
    if not how you need the output of your design, every 3rd/2nd clock cycle ? input to your square root module is coming from some other system or only your square root module ?
    above one is a good paper, instead of doing a single iteration, they are doing two iterations which will reduce the initial latency by half .

    what is the operating frequency of your design?

    regards



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