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  1. #1
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    xilinx timing analyze using modelsim SE

    Hello
    I'm trying to simulate a simple D Flip Flop in xilinx 14.7.I've wrote the testbench and I set the modelsim as simulator an I did the behavioral simulation without any problem but when I try to simulate the place & route simulation I can't see the result.
    This is my code :
    Code Verilog - [expand]
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    module dff(in, clk, reset, q);
     
        input in;
        input clk;
        input reset;
        output reg q;
         
         
     always @ (posedge clk or posedge reset)
      begin
       if(reset)
        begin
         q    = 1'b0;
         end
       else
        begin
          q    =  in;
         end
      end   
     
    and this is the testbench :
     
    module dff_test;
     
       localparam T=10;
        
        // Inputs
        reg in;
        reg clk;
        reg reset;
     
        // Outputs
        wire q;
     
        // Instantiate the Unit Under Test (UUT)
        dff uut (
            .in(in), 
            .clk(clk), 
            .reset(reset), 
            .q(q)
        );
        
        //defining clock
        always begin
         clk = 1'b0;
         #(T/2);
         clk = 1'b1;
         #(T/2);
       end
        
        //defining reset
        initial begin
         reset = 1'b1;
         #(T/2);
         reset = 1'b0;
         #(T/2);
        end
        
        //input vectors
        initial begin
         in = 1'b0;
         #(T);
         #(T/10);
         in = 1'b1;
         #(T);
         in = 1'b0;
         #(T);
        end
          
    endmodule
    this is behavioral result:
    Click image for larger version. 

Name:	Capture2.PNG 
Views:	4 
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ID:	140296

    this is timing result:
    Click image for larger version. 

Name:	Capture.PNG 
Views:	5 
Size:	29.7 KB 
ID:	140295

    - - - Updated - - -

    actually I should say ISE 14.7

    •   Alt3rd August 2017, 17:53

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  2. #2
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    Re: xilinx timing analyze using modelsim SE

    It looks like GSR is a weak 1 after 0 ns. It is initialized to 1 then 0 after 100 ns in the glbl.v, so you started applying your simulation stimulus too soon as it's still in reset.

    The reason the behavioral result works is due to being a behavioral description that does not require glbl.v so is not in reset when the D input has a 1 on it.

    You should also fix your reset it's way too short (it's not even a full clock cycle wide)


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